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MIPS DSP: add bitcast patterns between vectors and int.
author
Akira Hatanaka
<ahatanaka@mips.com>
Thu, 27 Sep 2012 01:56:38 +0000
(
01:56
+0000)
committer
Akira Hatanaka
<ahatanaka@mips.com>
Thu, 27 Sep 2012 01:56:38 +0000
(
01:56
+0000)
No test cases. These patterns will get tested along with dsp intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/Mips/MipsDSPInstrInfo.td
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diff --git
a/lib/Target/Mips/MipsDSPInstrInfo.td
b/lib/Target/Mips/MipsDSPInstrInfo.td
index 556cf6bc50003f20ff326ce4707c073b37574cbe..b9f40efbd1d5157a310fd660ebe53b5210e9f45b 100644
(file)
--- a/
lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/
lib/Target/Mips/MipsDSPInstrInfo.td
@@
-23,6
+23,16
@@
def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
Pat<pattern, result>, Requires<[pred]>;
class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
Pat<pattern, result>, Requires<[pred]>;
+class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
+ RegisterClass SrcRC> :
+ DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
+ (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
+
+def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
+def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
+def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
+def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
+
def : DSPPat<(v2i16 (load addr:$a)),
(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
def : DSPPat<(v4i8 (load addr:$a)),
def : DSPPat<(v2i16 (load addr:$a)),
(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
def : DSPPat<(v4i8 (load addr:$a)),