-#define CFGR 0x00
-#define SDBLR 0x04
-#define DMACR 0x08
-#define INTCR 0x0C
-#define INTSR 0x10
-#define XFER 0x18
-#define SMPDR 0x20
-
-#define SPDIF_CHNSR00_ADDR 0xC0
-#define SPDIF_CHNSR01_ADDR 0xC4
-#define SPDIF_CHNSR02_ADDR 0xC8
-#define SPDIF_CHNSR03_ADDR 0xCC
-#define SPDIF_CHNSR04_ADDR 0xD0
-#define SPDIF_CHNSR05_ADDR 0xD4
-#define SPDIF_CHNSR06_ADDR 0xD8
-#define SPDIF_CHNSR07_ADDR 0xDC
-#define SPDIF_CHNSR08_ADDR 0xE0
-#define SPDIF_CHNSR09_ADDR 0xE4
-#define SPDIF_CHNSR10_ADDR 0xE8
-#define SPDIF_CHNSR11_ADDR 0xEC
-
-#define SPDIF_BURST_INFO 0x100
-#define SPDIF_REPETTION 0x104
-
-#define DATA_OUTBUF 0x20
-
-#define SPDIF_CHANNEL_SEL_8CH ((0x2<<16)|(0x0<<0))
-#define SPDIF_CHANNEL_SEL_2CH ((0x2<<16)|(0x2<<0))
-
-/* burst_info bit0:6 AC-3:0x01, DTS-I -II -III:11,12,13 */
-#define burst_info_DATA_TYPE_AC3 0x01
-#define burst_info_DATA_TYPE_EAC3 0x15
-#define BURST_INFO_DATA_TYPE_DTS_I 0x0b
-
-#define CFGR_MASK 0x0ffffff
-#define CFGR_VALID_DATA_16bit (00)
-#define CFGR_VALID_DATA_20bit (01)
-#define CFGR_VALID_DATA_24bit (10)
-#define CFGR_VALID_DATA_MASK (11)
-
-#define CFGR_HALFWORD_TX_ENABLE (0x1<<2)
-#define CFGR_HALFWORD_TX_DISABLE (0x0<<2)
-#define CFGR_HALFWORD_TX_MASK (0x1<<2)
-
-#define CFGR_CLK_RATE_MASK (0xFF<<16)
-
-#define CFGR_JUSTIFIED_RIGHT (0<<3)
-#define CFGR_JUSTIFIED_LEFT (1<<3)
-#define CFGR_JUSTIFIED_MASK (1<<3)
-
-/* CSE:channel status enable */
-/* The bit should be set to 1 when the channel conveys non-linear PCM */
-#define CFGR_CSE_DISABLE (0<<6)
-#define CFGR_CSE_ENABLE (1<<6)
-#define CFGR_CSE_MASK (1<<6)
-
-#define CFGR_MCLK_CLR (1<<7)
-
-#define CFGR_LINEAR_PCM (0<<8)
-#define CFGR_NON_LINEAR_PCM (1<<8)
-#define CFGR_LINEAR_MASK (1<<8)
-
-/* support 7.1 amplifier,new */
-#define CFGR_PRE_CHANGE_ENALBLE (1<<9)
-#define CFGR_PRE_CHANGE_DISABLE (0<<9)
-#define CFGR_PRE_CHANGE_MASK (1<<9)
-
-#define XFER_TRAN_STOP (0)
-#define XFER_TRAN_START (1)
-#define XFER_MASK (1)
-
-#define DMACR_TRAN_DMA_DISABLE (0<<5)
-#define DMACR_TRAN_DMA_ENABLE (1<<5)
-#define DMACR_TRAN_DMA_CTL_MASK (1<<5)
-
-#define DMACR_TRAN_DATA_LEVEL 0x10
-#define DMACR_TRAN_DATA_LEVEL_MASK 0x1F
-#define DMACR_TRAN_DMA_MASK 0x3F
-
-/* Sample Date Buffer empty interrupt enable, new */
-#define INTCR_SDBEIE_DISABLE (0<<4)
-#define INTCR_SDBEIE_ENABLE (1<<4)
-#define INTCR_SDBEIE_MASK (1<<4)
+#define CFGR 0x00
+#define SDBLR 0x04
+#define DMACR 0x08
+#define INTCR 0x0C
+#define INTSR 0x10
+#define XFER 0x18
+#define SMPDR 0x20
+
+/* transfer configuration register */
+#define CFGR_VALID_DATA_16bit (0x0 << 0)
+#define CFGR_VALID_DATA_20bit (0x1 << 0)
+#define CFGR_VALID_DATA_24bit (0x2 << 0)
+#define CFGR_VALID_DATA_MASK (0x3 << 0)
+#define CFGR_HALFWORD_TX_ENABLE (0x1 << 2)
+#define CFGR_HALFWORD_TX_DISABLE (0x0 << 2)
+#define CFGR_HALFWORD_TX_MASK (0x1 << 2)
+#define CFGR_JUSTIFIED_RIGHT (0x0 << 3)
+#define CFGR_JUSTIFIED_LEFT (0x1 << 3)
+#define CFGR_JUSTIFIED_MASK (0x1 << 3)
+#define CFGR_CSE_DISABLE (0x0 << 6)
+#define CFGR_CSE_ENABLE (0x1 << 6)
+#define CFGR_CSE_MASK (0x1 << 6)
+#define CFGR_MCLK_CLR (0x1 << 7)
+#define CFGR_LINEAR_PCM (0x0 << 8)
+#define CFGR_NON_LINEAR_PCM (0x1 << 8)
+#define CFGR_LINEAR_MASK (0x1 << 8)
+#define CFGR_PRE_CHANGE_ENALBLE (0x1 << 9)
+#define CFGR_PRE_CHANGE_DISABLE (0x0 << 9)
+#define CFGR_PRE_CHANGE_MASK (0x1 << 9)
+#define CFGR_CLK_RATE_MASK (0xFF << 16)
+
+/* transfer start register */
+#define XFER_TRAN_STOP (0x0 << 0)
+#define XFER_TRAN_START (0x1 << 0)
+#define XFER_MASK (0x1 << 0)
+
+/* dma control register */
+#define DMACR_TRAN_DMA_DISABLE (0x0 << 5)
+#define DMACR_TRAN_DMA_ENABLE (0x1 << 5)
+#define DMACR_TRAN_DMA_CTL_MASK (0x1 << 5)
+#define DMACR_TRAN_DATA_LEVEL (0x10)
+#define DMACR_TRAN_DATA_LEVEL_MASK (0x1F)
+#define DMACR_TRAN_DMA_MASK (0x3F)
+#define DMA_DATA_LEVEL_16 (0x10)
+
+/* interrupt control register */
+#define INTCR_SDBEIE_DISABLE (0x0 << 4)
+#define INTCR_SDBEIE_ENABLE (0x1 << 4)
+#define INTCR_SDBEIE_MASK (0x1 << 4)