+/*
+ * I/O port register map
+ */
+#define PCL711_CTR0 0x00
+#define PCL711_CTR1 0x01
+#define PCL711_CTR2 0x02
+#define PCL711_CTRCTL 0x03
+#define PCL711_AD_LO 0x04
+#define PCL711_DA0_LO 0x04
+#define PCL711_AD_HI 0x05
+#define PCL711_DA0_HI 0x05
+#define PCL711_DI_LO 0x06
+#define PCL711_DA1_LO 0x06
+#define PCL711_DI_HI 0x07
+#define PCL711_DA1_HI 0x07
+#define PCL711_CLRINTR 0x08
+#define PCL711_GAIN 0x09
+#define PCL711_MUX 0x0a
+#define PCL711_MODE 0x0b
+#define PCL711_SOFTTRIG 0x0c
+#define PCL711_DO_LO 0x0d
+#define PCL711_DO_HI 0x0e