+ i2c0: i2c@11050000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x11050000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio", "sleep";
+ pinctrl-0 = <&i2c0_xfer>;
+ pinctrl-1 = <&i2c0_gpio>;
+ pinctrl-2 = <&i2c0_sleep>;
+ gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>,
+ <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates8 15>;
+ rockchip,check-idle = <1>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11060000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x11060000 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio", "sleep";
+ pinctrl-0 = <&i2c1_xfer>;
+ pinctrl-1 = <&i2c1_gpio>;
+ pinctrl-2 = <&i2c1_sleep>;
+ gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>,
+ <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates9 0>;
+ rockchip,check-idle = <1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11070000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x11070000 0x1000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio", "sleep";
+ pinctrl-0 = <&i2c2_xfer>;
+ pinctrl-1 = <&i2c2_gpio>;
+ pinctrl-2 = <&i2c2_sleep>;
+ gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>,
+ <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates9 1>;
+ rockchip,check-idle = <1>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11080000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x11080000 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio", "sleep";
+ pinctrl-0 = <&i2c3_xfer>;
+ pinctrl-1 = <&i2c3_gpio>;
+ pinctrl-2 = <&i2c3_sleep>;
+ gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>,
+ <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates9 2>;
+ rockchip,check-idle = <1>;
+ status = "disabled";
+ };
+