+ case ISD::SETCC: {
+ ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+ assert(MVT::isInteger(N->getOperand(0).getValueType()) && "FP numbers are unnecessary");
+ SDOperand Op1 = Select(N->getOperand(0));
+ SDOperand Op2 = Select(N->getOperand(1));
+ unsigned Opc = Alpha::WTF;
+ int dir;
+ switch (CC) {
+ default: N->dump(); assert(0 && "Unknown integer comparison!");
+ case ISD::SETEQ: Opc = Alpha::CMPEQ; dir=1; break;
+ case ISD::SETLT: Opc = Alpha::CMPLT; dir = 1; break;
+ case ISD::SETLE: Opc = Alpha::CMPLE; dir = 1; break;
+ case ISD::SETGT: Opc = Alpha::CMPLT; dir = 0; break;
+ case ISD::SETGE: Opc = Alpha::CMPLE; dir = 0; break;
+ case ISD::SETULT: Opc = Alpha::CMPULT; dir = 1; break;
+ case ISD::SETUGT: Opc = Alpha::CMPULT; dir = 0; break;
+ case ISD::SETULE: Opc = Alpha::CMPULE; dir = 1; break;
+ case ISD::SETUGE: Opc = Alpha::CMPULE; dir = 0; break;
+ case ISD::SETNE: {//Handle this one special
+ SDOperand Tmp = CurDAG->getTargetNode(Alpha::CMPEQ, MVT::i64, Op1, Op2);
+ CurDAG->SelectNodeTo(N, Alpha::CMPEQ, MVT::i64, CurDAG->getRegister(Alpha::R31, MVT::i64), Tmp);
+ return SDOperand(N, 0);
+ }
+ }
+ CurDAG->SelectNodeTo(N, Opc, MVT::i64, dir ? Op1 : Op2, dir ? Op2 : Op1);
+ return SDOperand(N, 0);
+ }
+
+ case ISD::BRCOND: {
+ SDOperand Chain = Select(N->getOperand(0));
+ SDOperand CC = Select(N->getOperand(1));
+ CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, Chain);
+ return SDOperand(N, 0);
+ }
+ case ISD::LOAD:
+ case ISD::EXTLOAD:
+ case ISD::ZEXTLOAD:
+ case ISD::SEXTLOAD: {
+ SDOperand Chain = Select(N->getOperand(0));
+ SDOperand Address = Select(N->getOperand(1));
+ unsigned opcode = N->getOpcode();
+ unsigned Opc = Alpha::WTF;
+ if (opcode == ISD::LOAD)
+ switch (N->getValueType(0)) {
+ default: N->dump(); assert(0 && "Bad load!");
+ case MVT::i64: Opc = Alpha::LDQ; break;
+ case MVT::f64: Opc = Alpha::LDT; break;
+ case MVT::f32: Opc = Alpha::LDS; break;
+ }
+ else
+ switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
+ default: N->dump(); assert(0 && "Bad sign extend!");
+ case MVT::i32: Opc = Alpha::LDL;
+ assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
+ case MVT::i16: Opc = Alpha::LDWU;
+ assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
+ case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
+ case MVT::i8: Opc = Alpha::LDBU;
+ assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
+ }
+
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+ getI64Imm(0), Address, Chain);
+ return SDOperand(N, Op.ResNo);
+ }
+