drm/i915/bdw: support GMS and GGMS changes

All the BARs have the ability to grow.

v2: Pulled out the simulator workaround to a separate patch.
Rebased.

v3: Rebase onto latest vlv patches from Jesse.

v4: Rebased on top of the early stolen quirk patch from Jesse.

v5: Use the new macro names.
s/INTEL_BDW_PCI_IDS_D/INTEL_BDW_D_IDS
s/INTEL_BDW_PCI_IDS_M/INTEL_BDW_M_IDS
It's Jesse's fault for not following the convention I originally set.

Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b3cd3ebae0774001391548d7cad0582fcbfeb50d..96f958d8cd450cb57b489ba9e37684387c297bb0 100644 (file)
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -313,6 +313,16 @@ static size_t __init gen6_stolen_size(int num, int slot, int func)
        return gmch_ctrl << 25; /* 32 MB units */
 }
 
        return gmch_ctrl << 25; /* 32 MB units */
 }
 

+static inline size_t gen8_stolen_size(int num, int slot, int func)
+{
+       u16 gmch_ctrl;
+
+       gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
+       gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
+       gmch_ctrl &= BDW_GMCH_GMS_MASK;
+       return gmch_ctrl << 25; /* 32 MB units */
+}
+

 typedef size_t (*stolen_size_fn)(int num, int slot, int func);
 
 static struct pci_device_id intel_stolen_ids[] __initdata = {
 typedef size_t (*stolen_size_fn)(int num, int slot, int func);
 
 static struct pci_device_id intel_stolen_ids[] __initdata = {


@@ -336,6 +346,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
        INTEL_IVB_D_IDS(gen6_stolen_size),
        INTEL_HSW_D_IDS(gen6_stolen_size),
        INTEL_HSW_M_IDS(gen6_stolen_size),
        INTEL_IVB_D_IDS(gen6_stolen_size),
        INTEL_HSW_D_IDS(gen6_stolen_size),
        INTEL_HSW_M_IDS(gen6_stolen_size),

+       INTEL_BDW_M_IDS(gen8_stolen_size),
+       INTEL_BDW_D_IDS(gen8_stolen_size)

 };
 
 static void __init intel_graphics_stolen(int num, int slot, int func)
 };
 
 static void __init intel_graphics_stolen(int num, int slot, int func)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7d5a51fea1bbbd1d287123ecdefd3cbe1d76a3ba..074aec11fc9b1c488a955d2321afdce1b9bfca97 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -869,6 +869,15 @@ static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
        return snb_gmch_ctl << 20;
 }
 
        return snb_gmch_ctl << 20;
 }
 

+static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
+{
+       bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
+       bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
+       if (bdw_gmch_ctl)
+               bdw_gmch_ctl = 1 << bdw_gmch_ctl;
+       return bdw_gmch_ctl << 20;
+}
+

 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 {
        snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 {
        snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;


@@ -876,6 +885,13 @@ static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
        return snb_gmch_ctl << 25; /* 32 MB units */
 }
 
        return snb_gmch_ctl << 25; /* 32 MB units */
 }
 

+static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
+{
+       bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
+       bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
+       return bdw_gmch_ctl << 25; /* 32 MB units */
+}
+

 static int gen6_gmch_probe(struct drm_device *dev,
                           size_t *gtt_total,
                           size_t *stolen,
 static int gen6_gmch_probe(struct drm_device *dev,
                           size_t *gtt_total,
                           size_t *stolen,


@@ -903,10 +919,16 @@ static int gen6_gmch_probe(struct drm_device *dev,
        if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
                pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
        pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
        if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
                pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
        pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);

-       gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);

 
 

-       *stolen = gen6_get_stolen_size(snb_gmch_ctl);
-       *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
+       if (IS_GEN8(dev)) {
+               gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+               *gtt_total = (gtt_size / 8) << PAGE_SHIFT;
+               *stolen = gen8_get_stolen_size(snb_gmch_ctl);
+       } else {
+               gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
+               *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
+               *stolen = gen6_get_stolen_size(snb_gmch_ctl);
+       }

 
        /* For Modern GENs the PTEs and register space are split in the BAR */
        gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 
        /* For Modern GENs the PTEs and register space are split in the BAR */
        gtt_bus_addr = pci_resource_start(dev->pdev, 0) +


@@ -916,6 +938,7 @@ static int gen6_gmch_probe(struct drm_device *dev,
        if (!dev_priv->gtt.gsm) {
                DRM_ERROR("Failed to map the gtt page table\n");
                return -ENOMEM;
        if (!dev_priv->gtt.gsm) {
                DRM_ERROR("Failed to map the gtt page table\n");
                return -ENOMEM;

+

        }
 
        ret = setup_scratch_page(dev);
        }
 
        ret = setup_scratch_page(dev);

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 3abfa6ea226edda57aed2b9efaf970dcae1d3c35..97d5497debc1c7dc0b7b6c75199810bf13b6c03f 100644 (file)
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -49,6 +49,10 @@ extern bool i915_gpu_turbo_disable(void);
 #define    SNB_GMCH_GGMS_MASK  0x3
 #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
 #define    SNB_GMCH_GMS_MASK    0x1f
 #define    SNB_GMCH_GGMS_MASK  0x3
 #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
 #define    SNB_GMCH_GMS_MASK    0x1f

+#define    BDW_GMCH_GGMS_SHIFT 6
+#define    BDW_GMCH_GGMS_MASK  0x3
+#define    BDW_GMCH_GMS_SHIFT   8
+#define    BDW_GMCH_GMS_MASK    0xff

 
 #define I830_GMCH_CTRL                 0x52
 
 
 #define I830_GMCH_CTRL                 0x52