+// Section A.27: Load Integer - p178
+def LDSBr : F3_1<3, 0b001001, "ldsb">; // ldsb [r+r], r
+def LDSBi : F3_2<3, 0b001001, "ldsb">; // ldsb [r+i], r
+def LDSHr : F3_1<3, 0b001010, "ldsh">; // ldsh [r+r], r
+def LDSHi : F3_2<3, 0b001010, "ldsh">; // ldsh [r+i], r
+def LDSWr : F3_1<3, 0b001000, "ldsw">; // ldsh [r+r], r
+def LDSWi : F3_2<3, 0b001000, "ldsw">; // ldsh [r+i], r
+def LDUBr : F3_1<3, 0b000001, "ldub">; // ldub [r+r], r
+def LDUBi : F3_2<3, 0b000001, "ldub">; // ldub [r+i], r
+def LDUHr : F3_1<3, 0b000010, "lduh">; // lduh [r+r], r
+def LDUHi : F3_2<3, 0b000010, "lduh">; // lduh [r+i], r
+// synonym: LD
+def LDUWr : F3_1<3, 0b000000, "lduw">; // lduw [r+r], r
+def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [r+i], r
+// LDD should no longer be used, LDX should be used instead
+def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [r+r], r
+def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [r+i], r
+//set isDeprecated = 1 in {
+// def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [r+r], r
+// def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [r+i], r
+//}
+
+// Section A.31: Logical operations
+def ANDr : F3_1<2, 0b000001, "and">; // and r, r, r
+def ANDi : F3_2<2, 0b000001, "and">; // and r, r, i
+def ANDccr : F3_1<2, 0b010001, "andcc">; // andcc r, r, r
+def ANDcci : F3_2<2, 0b010001, "andcc">; // andcc r, r, i
+def ANDNr : F3_1<2, 0b000101, "andn">; // andn r, r, r
+def ANDNi : F3_2<2, 0b000101, "andn">; // andn r, r, i
+def ANDNccr : F3_1<2, 0b010101, "andncc">; // andncc r, r, r
+def ANDNcci : F3_2<2, 0b010101, "andncc">; // andncc r, r, i
+
+def ORr : F3_1<2, 0b000010, "or">; // or r, r, r
+def ORi : F3_2<2, 0b000010, "or">; // or r, r, i
+def ORccr : F3_1<2, 0b010010, "orcc">; // orcc r, r, r
+def ORcci : F3_2<2, 0b010010, "orcc">; // orcc r, r, i
+def ORNr : F3_1<2, 0b000110, "orn">; // orn r, r, r
+def ORNi : F3_2<2, 0b000110, "orn">; // orn r, r, i
+def ORNccr : F3_1<2, 0b010110, "orncc">; // orncc r, r, r
+def ORNcci : F3_2<2, 0b010110, "orncc">; // orncc r, r, i
+
+def XORr : F3_1<2, 0b000011, "xor">; // xor r, r, r
+def XORi : F3_2<2, 0b000011, "xor">; // xor r, r, i
+def XORccr : F3_1<2, 0b010011, "xorcc">; // xorcc r, r, r
+def XORcci : F3_2<2, 0b010011, "xorcc">; // xorcc r, r, i
+def XNORr : F3_1<2, 0b000111, "xnor">; // xnor r, r, r
+def XNORi : F3_2<2, 0b000111, "xnor">; // xnor r, r, i
+def XNORccr : F3_1<2, 0b010111, "xnorcc">; // xnorcc r, r, r
+def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc r, r, i
+
+#if 0
+// Section A.33: Move Floating-Point Register on Condition (FMOVcc)
+// For integer condition codes
+def FMOVA : F4_7<2, 0b110101, 0b1000, "fmova">; // fmova r, r
+def FMOVN : F4_7<2, 0b110101, 0b0000, "fmovn">; // fmovn r, r
+def FMOVNE : F4_7<2, 0b110101, 0b1001, "fmovne">; // fmovne r, r
+def FMOVE : F4_7<2, 0b110101, 0b0000, "fmove">; // fmove r, r
+def FMOVG : F4_7<2, 0b110101, 0b1010, "fmovg">; // fmovg r, r
+def FMOVLE : F4_7<2, 0b110101, 0b0000, "fmovle">; // fmovle r, r
+def FMOVGE : F4_7<2, 0b110101, 0b1011, "fmovge">; // fmovge r, r
+def FMOVL : F4_7<2, 0b110101, 0b0011, "fmovl">; // fmovl r, r
+def FMOVGU : F4_7<2, 0b110101, 0b1100, "fmovgu">; // fmovgu r, r
+def FMOVLEU : F4_7<2, 0b110101, 0b0100, "fmovleu">; // fmovleu r, r
+def FMOVCC : F4_7<2, 0b110101, 0b1101, "fmovcc">; // fmovcc r, r
+def FMOVCS : F4_7<2, 0b110101, 0b0101, "fmovcs">; // fmovcs r, r
+def FMOVPOS : F4_7<2, 0b110101, 0b1110, "fmovpos">; // fmovpos r, r
+def FMOVNEG : F4_7<2, 0b110101, 0b0110, "fmovneg">; // fmovneg r, r
+def FMOVVC : F4_7<2, 0b110101, 0b1111, "fmovvc">; // fmovvc r, r
+def FMOVVS : F4_7<2, 0b110101, 0b0111, "fmovvs">; // fmovvs r, r
+
+// For floating-point condition codes
+def FMOVFA : F4_7<2, 0b110101, 0b0100, "fmovfa">; // fmovfa r, r
+def FMOVFN : F4_7<2, 0b110101, 0b0000, "fmovfn">; // fmovfa r, r
+def FMOVFU : F4_7<2, 0b110101, 0b0111, "fmovfu">; // fmovfu r, r
+def FMOVFG : F4_7<2, 0b110101, 0b0110, "fmovfg">; // fmovfg r, r
+def FMOVFUG : F4_7<2, 0b110101, 0b0101, "fmovfug">; // fmovfug r, r
+def FMOVFL : F4_7<2, 0b110101, 0b0100, "fmovfl">; // fmovfl r, r
+def FMOVFUL : F4_7<2, 0b110101, 0b0011, "fmovful">; // fmovful r, r
+def FMOVFLG : F4_7<2, 0b110101, 0b0010, "fmovflg">; // fmovflg r, r
+def FMOVFNE : F4_7<2, 0b110101, 0b0001, "fmovfne">; // fmovfne r, r
+def FMOVFE : F4_7<2, 0b110101, 0b1001, "fmovfe">; // fmovfe r, r
+def FMOVFUE : F4_7<2, 0b110101, 0b1010, "fmovfue">; // fmovfue r, r
+def FMOVGE : F4_7<2, 0b110101, 0b1011, "fmovge">; // fmovge r, r
+def FMOVFUGE : F4_7<2, 0b110101, 0b1100, "fmovfuge">; // fmovfuge r, r
+def FMOVFLE : F4_7<2, 0b110101, 0b1101, "fmovfle">; // fmovfle r, r
+def FMOVFULE : F4_7<2, 0b110101, 0b1110, "fmovfule">; // fmovfule r, r
+def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r
+#endif
+
+// Section A.37: Multiply and Divide (64-bit) - p199
+def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r
+def SDIVXr : F3_1<2, 0b101101, "sdivx">; // mulx r, r, r
+def UDIVXr : F3_1<2, 0b001101, "udivx">; // mulx r, r, r
+def MULXi : F3_2<2, 0b001001, "mulx">; // mulx r, i, r
+def SDIVXi : F3_2<2, 0b101101, "sdivx">; // mulx r, i, r
+def UDIVXi : F3_2<2, 0b001101, "udivx">; // mulx r, i, r
+
+// Section A.38: Multiply (32-bit) - p200
+// Not used in the Sparc backend?
+//set Inst{13} = 0 in {
+// def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
+// def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
+// def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r
+// def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r
+//}
+//set Inst{13} = 1 in {
+// def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r
+// def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r
+// def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
+// def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
+//}
+
+// Section A.40: No operation - p204
+// NOP is really a pseudo-instruction (special case of SETHI)
+set op2 = 0b100 in {
+ set rd = 0 in {
+ set imm = 0 in {
+ def NOP : F2_1<"nop">; // nop
+ }
+ }
+}
+
+// Section A.45: RETURN - p216