... which would only do one 32-bit XOR per loop iteration instead of two.
It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
... which would only do one 32-bit XOR per loop iteration instead of two.
It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
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+This is a form of idiom recognition for loops, the same thing that could be
+useful for recognizing memset/memcpy.
+
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These should turn into single 16-bit (unaligned?) loads on little/big endian
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These should turn into single 16-bit (unaligned?) loads on little/big endian
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-LSR should know what GPR types a target has. This code:
+LSR should know what GPR types a target has from TargetData. This code:
volatile short X, Y; // globals
volatile short X, Y; // globals
LSR should reuse the "+" IV for the exit test.
LSR should reuse the "+" IV for the exit test.
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Tail call elim should be more aggressive, checking to see if the call is
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Tail call elim should be more aggressive, checking to see if the call is