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2431223)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122545
91177308-0d34-0410-b5e6-
96231b3b80d8
/// isInstr - Return true if this SUnit refers to a machine instruction as
/// opposed to an SDNode.
/// isInstr - Return true if this SUnit refers to a machine instruction as
/// opposed to an SDNode.
- bool isInstr() const { return !Node; }
+ bool isInstr() const { return Instr; }
/// setInstr - Assign the instruction for the SUnit.
/// This may be used during post-regalloc scheduling.
/// setInstr - Assign the instruction for the SUnit.
/// This may be used during post-regalloc scheduling.
/// Check to see if any of the pending instructions are ready to issue. If
/// so, add them to the available queue.
void ScheduleDAGRRList::ReleasePending() {
/// Check to see if any of the pending instructions are ready to issue. If
/// so, add them to the available queue.
void ScheduleDAGRRList::ReleasePending() {
- assert(!EnableSchedCycles && "requires --enable-sched-cycles" );
+ if (!EnableSchedCycles) {
+ assert(PendingQueue.empty() && "pending instrs not allowed in this mode");
+ return;
+ }
// If the available queue is empty, it is safe to reset MinAvailableCycle.
if (AvailableQueue->empty())
// If the available queue is empty, it is safe to reset MinAvailableCycle.
if (AvailableQueue->empty())
RestoreHazardCheckerBottomUp();
RestoreHazardCheckerBottomUp();
- if (EnableSchedCycles)
- ReleasePending();