Change-Id: I9205286f7b4c0d7ecba3bb08a45af3f49225abe5
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
unsigned long prate)
{
u32 ret;
unsigned long prate)
{
u32 ret;
+ u32 lcdc_type;
+
+ lcdc_type = rk_drm_get_lcdc_type();
ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
if (ret) {
ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
if (ret) {
struct arm_smccc_res res;
struct rk3368_dram_timing *dram_timing;
struct clk *pclk_phy, *pclk_upctl;
struct arm_smccc_res res;
struct rk3368_dram_timing *dram_timing;
struct clk *pclk_phy, *pclk_upctl;
+ struct drm_device *drm = drm_device_get_by_name("rockchip");
int ret;
u32 dram_spd_bin;
u32 addr_mcu_el3;
u32 dclk_mode;
u32 lcdc_type;
int ret;
u32 dram_spd_bin;
u32 addr_mcu_el3;
u32 dclk_mode;
u32 lcdc_type;
+ if (!drm) {
+ dev_err(dev, "Get drm_device fail\n");
+ return -EPROBE_DEFER;
+ }
+
pclk_phy = devm_clk_get(dev, "pclk_phy");
if (IS_ERR(pclk_phy)) {
dev_err(dev, "Cannot get the clk pclk_phy\n");
pclk_phy = devm_clk_get(dev, "pclk_phy");
if (IS_ERR(pclk_phy)) {
dev_err(dev, "Cannot get the clk pclk_phy\n");
if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
scpi_ddr_dclk_mode(dclk_mode);
if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
scpi_ddr_dclk_mode(dclk_mode);
+ lcdc_type = rk_drm_get_lcdc_type();
if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
addr_mcu_el3))
if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
addr_mcu_el3))