+ return 0;
+}
+
+static void rockchip_dsi_set_hs_clk(struct dw_mipi_dsi *dsi)
+{
+ int ret;
+ unsigned long target_mbps;
+ unsigned long bw, rate;
+
+ target_mbps = rockchip_dsi_calc_bandwidth(dsi);
+ bw = target_mbps * USEC_PER_SEC;
+
+ rate = clk_round_rate(dsi->dphy.hs_clk, bw);
+ ret = clk_set_rate(dsi->dphy.hs_clk, rate);
+ if (ret)
+ dev_err(dsi->dev, "failed to set hs clock rate: %lu\n",
+ rate);
+
+ clk_prepare_enable(dsi->dphy.hs_clk);
+
+ dsi->lane_mbps = rate / USEC_PER_SEC;