The PHY registers are now being controlled from the connected phydev,
so there shouldn't be any reason for the et131x code to perform any
extra setup. Removing the interrupt setup code, and register defines
that are now unused.
On testing, no changes in behaviour were experienced.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
*/
static void et131x_xcvr_init(struct et131x_adapter *adapter)
{
*/
static void et131x_xcvr_init(struct et131x_adapter *adapter)
{
- et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr);
- et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr);
-
- /* Set the link status interrupt only. Bad behavior when link status
- * and auto neg are set, we run into a nested interrupt problem
- */
- imr |= (ET_PHY_INT_MASK_AUTONEGSTAT |
- ET_PHY_INT_MASK_LINKSTAT |
- ET_PHY_INT_MASK_ENABLE);
-
- et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr);
-
/* Set the LED behavior such that LED 1 indicates speed (off =
* 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
* link and activity (on for link, blink off for activity).
/* Set the LED behavior such that LED 1 indicates speed (off =
* 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
* link and activity (on for link, blink off for activity).
- * et131x_configure_global_regs - configure JAGCore global regs
+ * et131x_configure_global_regs - configure JAGCore global regs
* @adapter: pointer to our adapter structure
*
* Used to configure the global registers on the JAGCore
* @adapter: pointer to our adapter structure
*
* Used to configure the global registers on the JAGCore
-#define ET_PHY_INT_MASK_AUTONEGSTAT 0x0100
-#define ET_PHY_INT_MASK_LINKSTAT 0x0004
-#define ET_PHY_INT_MASK_ENABLE 0x0001
-
/* MI Register 25: Interrupt Status Reg(0x19)
* 15-10: reserved
* 9: mdio_sync_lost
/* MI Register 25: Interrupt Status Reg(0x19)
* 15-10: reserved
* 9: mdio_sync_lost