The latest Tegra clk pull had some problems. Fix them.
drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static?
drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting
drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td->i2c_lut[0]' is never less than zero.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
- val = regulator_list_hardware_vsel(td->vdd_reg,
+ val = regulator_list_hardware_vsel(td->vdd_reg,
td->i2c_lut[lut_index]);
__raw_writel(val, td->lut_base + i * 4);
}
td->i2c_lut[lut_index]);
__raw_writel(val, td->lut_base + i * 4);
}
int selector;
unsigned long rate;
struct dev_pm_opp *opp;
int selector;
unsigned long rate;
struct dev_pm_opp *opp;
v_max = dev_pm_opp_get_voltage(opp);
v = td->soc->min_millivolts * 1000;
v_max = dev_pm_opp_get_voltage(opp);
v = td->soc->min_millivolts * 1000;
- td->i2c_lut[0] = find_vdd_map_entry_exact(td, v);
- if (td->i2c_lut[0] < 0)
+ lut = find_vdd_map_entry_exact(td, v);
+ if (lut < 0)
for (j = 1, rate = 0; ; rate++) {
opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
for (j = 1, rate = 0; ; rate++) {
opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
*
* Assert the reset line of the DFLL's DVCO. No return value.
*/
*
* Assert the reset line of the DFLL's DVCO. No return value.
*/
-void tegra124_clock_assert_dfll_dvco_reset(void)
+static void tegra124_clock_assert_dfll_dvco_reset(void)
* Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
* operate. No return value.
*/
* Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
* operate. No return value.
*/
-void tegra124_clock_deassert_dfll_dvco_reset(void)
+static void tegra124_clock_deassert_dfll_dvco_reset(void)
tegra124_car_barrier();
}
tegra124_car_barrier();
}
-int tegra124_reset_assert(unsigned long id)
+static int tegra124_reset_assert(unsigned long id)
{
if (id == TEGRA124_RST_DFLL_DVCO)
tegra124_clock_assert_dfll_dvco_reset();
{
if (id == TEGRA124_RST_DFLL_DVCO)
tegra124_clock_assert_dfll_dvco_reset();
-int tegra124_reset_deassert(unsigned long id)
+static int tegra124_reset_deassert(unsigned long id)
{
if (id == TEGRA124_RST_DFLL_DVCO)
tegra124_clock_deassert_dfll_dvco_reset();
{
if (id == TEGRA124_RST_DFLL_DVCO)
tegra124_clock_deassert_dfll_dvco_reset();