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RK3126/3126B DDR:fix ddr DQS1 drv set err
author
typ
<typ@rock-chips.com>
Mon, 8 Dec 2014 02:50:18 +0000
(10:50 +0800)
committer
typ
<typ@rock-chips.com>
Mon, 8 Dec 2014 02:56:00 +0000
(10:56 +0800)
arch/arm/mach-rockchip/ddr_rk3126b.c
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diff --git
a/arch/arm/mach-rockchip/ddr_rk3126b.c
b/arch/arm/mach-rockchip/ddr_rk3126b.c
index e747f9baff43311cb10f870df79192d758bf8a8a..5e1bc097aee951ff3405cbe3713a6fa88625c318 100755
(executable)
--- a/
arch/arm/mach-rockchip/ddr_rk3126b.c
+++ b/
arch/arm/mach-rockchip/ddr_rk3126b.c
@@
-1032,7
+1032,7
@@
static void __sramfunc ddr_set_dll_bypass(uint32 freq)
uint32 phase;
if (freq < 350) {
phase = 3;
uint32 phase;
if (freq < 350) {
phase = 3;
- } else if (freq < 6
00
) {
+ } else if (freq < 6
66
) {
phase = 2;
} else
phase = 1;
phase = 2;
} else
phase = 1;
@@
-1521,7
+1521,7
@@
static void __sramfunc ddr_update_odt(void)
pPHY_Reg->PHY_REG22 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*clk drv*/
pPHY_Reg->PHY_REG25 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*DQS0 drv*/
pPHY_Reg->PHY_REG22 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*clk drv*/
pPHY_Reg->PHY_REG25 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*DQS0 drv*/
- pPHY_Reg->PHY_REG
3
6 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*DQS1 drv*/
+ pPHY_Reg->PHY_REG
2
6 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*DQS1 drv*/
dsb();
}
dsb();
}