ARM fixup encoding for direct call instructions (BL).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 3465e9879e4122e02bb1c681aaac44feec2421e7..b8948322c20751c358f4305d568c60831a8ca61b 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -278,6 +278,12 @@ def brtarget : Operand<OtherVT> {
   string EncoderMethod = "getBranchTargetOpValue";
 }
 
   string EncoderMethod = "getBranchTargetOpValue";
 }
 

+// Call target.
+def bltarget : Operand<i32> {
+  // Encoded the same as branch targets.
+  string EncoderMethod = "getBranchTargetOpValue";
+}
+

 // A list of registers separated by comma. Used by load/store multiple.
 def reglist : Operand<i32> {
   string EncoderMethod = "getRegisterListOpValue";
 // A list of registers separated by comma. Used by load/store multiple.
 def reglist : Operand<i32> {
   string EncoderMethod = "getRegisterListOpValue";


@@ -1198,18 +1204,22 @@ let isCall = 1,
           D0,  D1,  D2,  D3,  D4,  D5,  D6,  D7,
           D16, D17, D18, D19, D20, D21, D22, D23,
           D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
           D0,  D1,  D2,  D3,  D4,  D5,  D6,  D7,
           D16, D17, D18, D19, D20, D21, D22, D23,
           D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {

-  def BL  : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
+  def BL  : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),

                 IIC_Br, "bl\t$func",
                 [(ARMcall tglobaladdr:$func)]>,
             Requires<[IsARM, IsNotDarwin]> {
     let Inst{31-28} = 0b1110;
                 IIC_Br, "bl\t$func",
                 [(ARMcall tglobaladdr:$func)]>,
             Requires<[IsARM, IsNotDarwin]> {
     let Inst{31-28} = 0b1110;

-    // FIXME: Encoding info for $func. Needs fixups bits.
+    bits<24> func;
+    let Inst{23-0} = func;

   }
 
   }
 

-  def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
+  def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),

                    IIC_Br, "bl", "\t$func",
                    [(ARMcall_pred tglobaladdr:$func)]>,
                    IIC_Br, "bl", "\t$func",
                    [(ARMcall_pred tglobaladdr:$func)]>,

-                Requires<[IsARM, IsNotDarwin]>;
+                Requires<[IsARM, IsNotDarwin]> {
+    bits<24> func;
+    let Inst{23-0} = func;
+  }

 
   // ARMv5T and above
   def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
 
   // ARMv5T and above
   def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,


@@ -1249,17 +1259,21 @@ let isCall = 1,
           D0,  D1,  D2,  D3,  D4,  D5,  D6,  D7,
           D16, D17, D18, D19, D20, D21, D22, D23,
           D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
           D0,  D1,  D2,  D3,  D4,  D5,  D6,  D7,
           D16, D17, D18, D19, D20, D21, D22, D23,
           D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {

-  def BLr9  : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
+  def BLr9  : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),

                 IIC_Br, "bl\t$func",
                 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
     let Inst{31-28} = 0b1110;
                 IIC_Br, "bl\t$func",
                 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
     let Inst{31-28} = 0b1110;

-    // FIXME: Encoding info for $func. Needs fixups bits.
+    bits<24> func;
+    let Inst{23-0} = func;

   }
 
   }
 

-  def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
+  def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),

                    IIC_Br, "bl", "\t$func",
                    [(ARMcall_pred tglobaladdr:$func)]>,
                    IIC_Br, "bl", "\t$func",
                    [(ARMcall_pred tglobaladdr:$func)]>,

-                  Requires<[IsARM, IsDarwin]>;
+                  Requires<[IsARM, IsDarwin]> {
+    bits<24> func;
+    let Inst{23-0} = func;
+  }

 
   // ARMv5T and above
   def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
 
   // ARMv5T and above
   def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,

diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp
index 9b002eeea11b6766dd4c8f7912c2830b0b9c4e8b..78d3510ca6dc65a84e11039ff1eca7b59641db63 100644 (file)
--- a/utils/TableGen/EDEmitter.cpp
+++ b/utils/TableGen/EDEmitter.cpp
@@ -322,6 +322,7 @@ static int X86TypeFromOpName(LiteralConstantEmitter *type,
   PCR("offset32");
   PCR("offset64");
   PCR("brtarget");
   PCR("offset32");
   PCR("offset64");
   PCR("brtarget");

+  PCR("bltarget");

 
   return 1;
 }
 
   return 1;
 }


@@ -584,6 +585,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   IMM("neon_vcvt_imm32");
 
   MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
   IMM("neon_vcvt_imm32");
 
   MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?

+  MISC("bltarget", "kOperandTypeARMBranchTarget");                // ?

   MISC("so_reg", "kOperandTypeARMSoReg");                         // R, R, I
   MISC("shift_so_reg", "kOperandTypeARMSoReg");                   // R, R, I
   MISC("t2_so_reg", "kOperandTypeThumb2SoReg");                   // R, I
   MISC("so_reg", "kOperandTypeARMSoReg");                         // R, R, I
   MISC("shift_so_reg", "kOperandTypeARMSoReg");                   // R, R, I
   MISC("t2_so_reg", "kOperandTypeThumb2SoReg");                   // R, I