+
+static int rk312x_mipi_dsi_phy_set_gotp(struct dsi *dsi, u32 offset, int n)
+{
+ u32 val = 0, temp = 0, Tlpx = 0;
+ u32 ddr_clk = dsi->phy.ddr_clk;
+ u32 Ttxbyte_clk = dsi->phy.Ttxbyte_clk;
+ u32 Tsys_clk = dsi->phy.Tsys_clk;
+ u32 Ttxclkesc = dsi->phy.Ttxclkesc;
+ printk("%s : ddr_clk %d\n",__func__, ddr_clk);
+ switch(offset) {
+ case DPHY_CLOCK_OFFSET:
+ MIPI_DBG("******set DPHY_CLOCK_OFFSET gotp******\n");
+ break;
+ case DPHY_LANE0_OFFSET:
+ MIPI_DBG("******set DPHY_LANE0_OFFSET gotp******\n");
+ break;
+ case DPHY_LANE1_OFFSET:
+ MIPI_DBG("******set DPHY_LANE1_OFFSET gotp******\n");
+ break;
+ case DPHY_LANE2_OFFSET:
+ MIPI_DBG("******set DPHY_LANE2_OFFSET gotp******\n");
+ break;
+ case DPHY_LANE3_OFFSET:
+ MIPI_DBG("******set DPHY_LANE3_OFFSET gotp******\n");
+ break;
+ default:
+ break;
+ }
+
+ if(ddr_clk < 110 * MHz)
+ val = 0;
+ else if(ddr_clk < 150 * MHz)
+ val = 1;
+ else if(ddr_clk < 200 * MHz)
+ val = 2;
+ else if(ddr_clk < 250 * MHz)
+ val = 3;
+ else if(ddr_clk < 300 * MHz)
+ val = 4;
+ else if(ddr_clk < 400 * MHz)
+ val = 5;
+ else if(ddr_clk < 500 * MHz)
+ val = 6;
+ else if(ddr_clk < 600 * MHz)
+ val = 7;
+ else if(ddr_clk < 700 * MHz)
+ val = 8;
+ else if(ddr_clk < 800 * MHz)
+ val = 9;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 10;
+ printk("%s reg_ths_settle = 0x%x\n",__func__, val);
+ rk32_dsi_set_bits(dsi, val, reg_ths_settle + offset);
+
+ if(ddr_clk < 110 * MHz)
+ val = 0x20;
+ else if(ddr_clk < 150 * MHz)
+ val = 0x06;
+ else if(ddr_clk < 200 * MHz)
+ val = 0x18;
+ else if(ddr_clk < 250 * MHz)
+ val = 0x05;
+ else if(ddr_clk < 300 * MHz)
+ val = 0x51;
+ else if(ddr_clk < 400 * MHz)
+ val = 0x64;
+ else if(ddr_clk < 500 * MHz)
+ val = 0x59;
+ else if(ddr_clk < 600 * MHz)
+ val = 0x6a;
+ else if(ddr_clk < 700 * MHz)
+ val = 0x3e;
+ else if(ddr_clk < 800 * MHz)
+ val = 0x21;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 0x09;
+ printk("%s reg_hs_ths_prepare = 0x%x\n",__func__, val);
+ rk32_dsi_set_bits(dsi, val, reg_hs_ths_prepare + offset);
+
+ if(offset != DPHY_CLOCK_OFFSET) {
+
+ if(ddr_clk < 110 * MHz)
+ val = 2;
+ else if(ddr_clk < 150 * MHz)
+ val = 3;
+ else if(ddr_clk < 200 * MHz)
+ val = 4;
+ else if(ddr_clk < 250 * MHz)
+ val = 5;
+ else if(ddr_clk < 300 * MHz)
+ val = 6;
+ else if(ddr_clk < 400 * MHz)
+ val = 7;
+ else if(ddr_clk < 500 * MHz)
+ val = 7;
+ else if(ddr_clk < 600 * MHz)
+ val = 8;
+ else if(ddr_clk < 700 * MHz)
+ val = 8;
+ else if(ddr_clk < 800 * MHz)
+ val = 9;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 9;
+ } else {
+
+ if(ddr_clk < 110 * MHz)
+ val = 0x16;
+ else if(ddr_clk < 150 * MHz)
+ val = 0x16;
+ else if(ddr_clk < 200 * MHz)
+ val = 0x17;
+ else if(ddr_clk < 250 * MHz)
+ val = 0x17;
+ else if(ddr_clk < 300 * MHz)
+ val = 0x18;
+ else if(ddr_clk < 400 * MHz)
+ val = 0x19;
+ else if(ddr_clk < 500 * MHz)
+ val = 0x1b;
+ else if(ddr_clk < 600 * MHz)
+ val = 0x1d;
+ else if(ddr_clk < 700 * MHz)
+ val = 0x1e;
+ else if(ddr_clk < 800 * MHz)
+ val = 0x1f;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 0x20;
+ }
+ printk("%s reg_hs_the_zero = 0x%x\n",__func__, val);
+ rk32_dsi_set_bits(dsi, val, reg_hs_the_zero + offset);
+
+ if(ddr_clk < 110 * MHz)
+ val = 0x22;
+ else if(ddr_clk < 150 * MHz)
+ val = 0x45;
+ else if(ddr_clk < 200 * MHz)
+ val = 0x0b;
+ else if(ddr_clk < 250 * MHz)
+ val = 0x16;
+ else if(ddr_clk < 300 * MHz)
+ val = 0x2c;
+ else if(ddr_clk < 400 * MHz)
+ val = 0x33;
+ else if(ddr_clk < 500 * MHz)
+ val = 0x4e;
+ else if(ddr_clk < 600 * MHz)
+ val = 0x3a;
+ else if(ddr_clk < 700 * MHz)
+ val = 0x6a;
+ else if(ddr_clk < 800 * MHz)
+ val = 0x29;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 0x21; //0x27
+
+ printk("%s reg_hs_ths_trail = 0x%x\n",__func__, val);
+
+ rk32_dsi_set_bits(dsi, val, reg_hs_ths_trail + offset);
+ val = 120000 / Ttxbyte_clk + 1;
+ MIPI_DBG("reg_hs_ths_exit: %d, %d\n", val, val*Ttxbyte_clk/1000);
+ rk32_dsi_set_bits(dsi, val, reg_hs_ths_exit + offset);
+
+ if(offset == DPHY_CLOCK_OFFSET) {
+ val = (60000 + 52*dsi->phy.UI) / Ttxbyte_clk + 1;
+ MIPI_DBG("reg_hs_tclk_post: %d, %d\n", val, val*Ttxbyte_clk/1000);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tclk_post + offset);
+ val = 10*dsi->phy.UI / Ttxbyte_clk + 1;
+ MIPI_DBG("reg_hs_tclk_pre: %d, %d\n", val, val*Ttxbyte_clk/1000);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tclk_pre + offset);
+ }
+
+ val = 1010000000 / Tsys_clk + 1;
+ MIPI_DBG("reg_hs_twakup: %d, %d\n", val, val*Tsys_clk/1000);
+ if(val > 0x3ff) {
+ val = 0x2ff;
+ MIPI_DBG("val is too large, 0x3ff is the largest\n");
+ }
+ temp = (val >> 8) & 0x03;
+ val &= 0xff;
+ rk32_dsi_set_bits(dsi, temp, reg_hs_twakup_h + offset);
+ rk32_dsi_set_bits(dsi, val, reg_hs_twakup_l + offset);
+
+ if(Ttxclkesc > 50000) {
+ val = 2*Ttxclkesc;
+ MIPI_DBG("Ttxclkesc:%d\n", Ttxclkesc);
+ }
+ val = val / Ttxbyte_clk;
+ Tlpx = val*Ttxbyte_clk;
+ MIPI_DBG("reg_hs_tlpx: %d, %d\n", val, Tlpx);
+ val -= 2;
+ rk32_dsi_set_bits(dsi, val, reg_hs_tlpx + offset);
+
+ Tlpx = 2*Ttxclkesc;
+ val = 4*Tlpx / Ttxclkesc;
+ MIPI_DBG("reg_hs_tta_go: %d, %d\n", val, val*Ttxclkesc);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tta_go + offset);
+ val = 3 * Tlpx / 2 / Ttxclkesc;
+ MIPI_DBG("reg_hs_tta_sure: %d, %d\n", val, val*Ttxclkesc);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tta_sure + offset);
+ val = 5 * Tlpx / Ttxclkesc;
+ MIPI_DBG("reg_hs_tta_wait: %d, %d\n", val, val*Ttxclkesc);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tta_wait + offset);
+ return 0;
+}
+