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7a970d7)
This patch adds the L2 cache topology on RK3368.
RK3368 has two clusters, each cluster has its own L2 cache.
Change-Id: Ibee5a39889d4924e439c9b0c249df052f63e9242
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
#cooling-cells = <2>; /* min followed by max */
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
#cooling-cells = <2>; /* min followed by max */
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
#cooling-cells = <2>; /* min followed by max */
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
#cooling-cells = <2>; /* min followed by max */
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
reg = <0x0 0x102>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
reg = <0x0 0x102>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
reg = <0x0 0x103>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
reg = <0x0 0x103>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
+
+ cluster0_l2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ cluster1_l2: l2-cache1 {
+ compatible = "cache";
+ };
};
cluster0_opp: opp_table0 {
};
cluster0_opp: opp_table0 {