The main register class may have been inflated by live range splitting, so that
register class is not necessarily valid for the snippet instructions.
Use the original register class for the stack slot interval.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128351
91177308-0d34-0410-b5e6-
96231b3b80d8
// Variables that are valid during spill(), but used by multiple methods.
LiveRangeEdit *Edit;
// Variables that are valid during spill(), but used by multiple methods.
LiveRangeEdit *Edit;
- const TargetRegisterClass *RC;
+ LiveInterval *StackInt;
int StackSlot;
unsigned Original;
int StackSlot;
unsigned Original;
// Conservatively extend the stack slot range to the range of the original
// value. We may be able to do better with stack slot coloring by being more
// careful here.
// Conservatively extend the stack slot range to the range of the original
// value. We may be able to do better with stack slot coloring by being more
// careful here.
- LiveInterval &StackInt = LSS.getInterval(StackSlot);
+ assert(StackInt && "No stack slot assigned yet.");
LiveInterval &OrigLI = LIS.getInterval(Original);
VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
LiveInterval &OrigLI = LIS.getInterval(Original);
VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
- StackInt.MergeValueInAsValue(OrigLI, OrigVNI, StackInt.getValNumInfo(0));
+ StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
// Already spilled everywhere.
if (SVI.AllDefsAreReloads)
// Already spilled everywhere.
if (SVI.AllDefsAreReloads)
++MII;
}
// Insert spill without kill flag immediately after def.
++MII;
}
// Insert spill without kill flag immediately after def.
- TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot, RC, &TRI);
+ TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
+ MRI.getRegClass(SVI.SpillReg), &TRI);
--MII; // Point to store instruction.
LIS.InsertMachineInstrInMaps(MII);
VRM.addSpillSlotUse(StackSlot, MII);
--MII; // Point to store instruction.
LIS.InsertMachineInstrInMaps(MII);
VRM.addSpillSlotUse(StackSlot, MII);
assert(VNI && "Missing value");
SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
WorkList.push_back(std::make_pair(&SLI, VNI));
assert(VNI && "Missing value");
SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
WorkList.push_back(std::make_pair(&SLI, VNI));
- LiveInterval &StackInt = LSS.getInterval(StackSlot);
+ assert(StackInt && "No stack slot assigned yet.");
continue;
// Add all of VNI's live range to StackInt.
continue;
// Add all of VNI's live range to StackInt.
- StackInt.MergeValueInAsValue(*LI, VNI, StackInt.getValNumInfo(0));
- DEBUG(dbgs() << "Merged to stack int: " << StackInt << '\n');
+ StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
+ DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
// Find all spills and copies of VNI.
for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
// Find all spills and copies of VNI.
for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
MachineBasicBlock::iterator MI) {
MachineBasicBlock &MBB = *MI->getParent();
SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
MachineBasicBlock::iterator MI) {
MachineBasicBlock &MBB = *MI->getParent();
SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
- TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot, RC, &TRI);
+ TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
+ MRI.getRegClass(NewLI.reg), &TRI);
--MI; // Point to load instruction.
SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
VRM.addSpillSlotUse(StackSlot, MI);
--MI; // Point to load instruction.
SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
VRM.addSpillSlotUse(StackSlot, MI);
assert(VNI && VNI->def.getDefIndex() == Idx && "Inconsistent VNInfo");
Idx = VNI->def;
assert(VNI && VNI->def.getDefIndex() == Idx && "Inconsistent VNInfo");
Idx = VNI->def;
- TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot, RC, &TRI);
+ TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
+ MRI.getRegClass(NewLI.reg), &TRI);
--MI; // Point to store instruction.
SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
VRM.addSpillSlotUse(StackSlot, MI);
--MI; // Point to store instruction.
SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
VRM.addSpillSlotUse(StackSlot, MI);
// Allocate interval around instruction.
// FIXME: Infer regclass from instruction alone.
// Allocate interval around instruction.
// FIXME: Infer regclass from instruction alone.
- LiveInterval &NewLI = Edit->create(LIS, VRM);
+ LiveInterval &NewLI = Edit->createFrom(Reg, LIS, VRM);
NewLI.markNotSpillable();
if (Reads)
NewLI.markNotSpillable();
if (Reads)
// Share a stack slot among all descendants of Original.
Original = VRM.getOriginal(edit.getReg());
StackSlot = VRM.getStackSlot(Original);
// Share a stack slot among all descendants of Original.
Original = VRM.getOriginal(edit.getReg());
StackSlot = VRM.getStackSlot(Original);
DEBUG(dbgs() << "Inline spilling "
<< MRI.getRegClass(edit.getReg())->getName()
DEBUG(dbgs() << "Inline spilling "
<< MRI.getRegClass(edit.getReg())->getName()
if (Edit->getParent().empty())
return;
if (Edit->getParent().empty())
return;
- RC = MRI.getRegClass(edit.getReg());
-
- if (StackSlot == VirtRegMap::NO_STACK_SLOT)
+ // Update LiveStacks now that we are committed to spilling.
+ if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
StackSlot = VRM.assignVirt2StackSlot(Original);
StackSlot = VRM.assignVirt2StackSlot(Original);
+ StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
+ StackInt->getNextValue(SlotIndex(), 0, LSS.getVNInfoAllocator());
+ } else
+ StackInt = &LSS.getInterval(StackSlot);
if (Original != edit.getReg())
VRM.assignVirt2StackSlot(edit.getReg(), StackSlot);
if (Original != edit.getReg())
VRM.assignVirt2StackSlot(edit.getReg(), StackSlot);
- // Update LiveStacks now that we are committed to spilling.
- LiveInterval &stacklvr = LSS.getOrCreateInterval(StackSlot, RC);
- if (!stacklvr.hasAtLeastOneValue())
- stacklvr.getNextValue(SlotIndex(), 0, LSS.getVNInfoAllocator());
+ assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
- stacklvr.MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]),
- stacklvr.getValNumInfo(0));
- DEBUG(dbgs() << "Merged spilled regs: " << stacklvr << '\n');
+ StackInt->MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]),
+ StackInt->getValNumInfo(0));
+ DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
// Spill around uses of all RegsToSpill.
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
// Spill around uses of all RegsToSpill.
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
/// live range trimmed or entirely removed.
SmallPtrSet<const VNInfo*,4> rematted_;
/// live range trimmed or entirely removed.
SmallPtrSet<const VNInfo*,4> rematted_;
- /// createFrom - Create a new virtual register based on OldReg.
- LiveInterval &createFrom(unsigned, LiveIntervals&, VirtRegMap &);
-
/// scanRemattable - Identify the parent_ values that may rematerialize.
void scanRemattable(LiveIntervals &lis,
const TargetInstrInfo &tii,
/// scanRemattable - Identify the parent_ values that may rematerialize.
void scanRemattable(LiveIntervals &lis,
const TargetInstrInfo &tii,
+ /// createFrom - Create a new virtual register based on OldReg.
+ LiveInterval &createFrom(unsigned OldReg, LiveIntervals&, VirtRegMap&);
+
/// create - Create a new register with the same class and original slot as
/// parent.
LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) {
/// create - Create a new register with the same class and original slot as
/// parent.
LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) {