git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198008
91177308-0d34-0410-b5e6-
96231b3b80d8
EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
if (!VT.isVector())
EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
if (!VT.isVector())
+ return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
- const TargetMachine &TM = getTargetMachine();
- if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
+ if (Subtarget->hasAVX512())
switch(VT.getVectorNumElements()) {
case 8: return MVT::v8i1;
case 16: return MVT::v16i1;
switch(VT.getVectorNumElements()) {
case 8: return MVT::v8i1;
case 16: return MVT::v16i1;
return VT.changeVectorElementTypeToInteger();
}
return VT.changeVectorElementTypeToInteger();
}
if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
- assert((VT == MVT::i8 || (Subtarget->hasAVX512() && VT == MVT::i1))
+ assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
&& "SetCC type must be 8-bit or 1-bit integer");
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
&& "SetCC type must be 8-bit or 1-bit integer");
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
if (!Invert) return Op0;
CCode = X86::GetOppositeBranchCondition(CCode);
if (!Invert) return Op0;
CCode = X86::GetOppositeBranchCondition(CCode);
- return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
+ return DAG.getNode(X86ISD::SETCC, dl, VT,
DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
}
}
DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
}
}
SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
- MVT SetCCVT = Subtarget->hasAVX512() ? MVT::i1 : MVT::i8;
- return DAG.getNode(X86ISD::SETCC, dl, SetCCVT,
+ return DAG.getNode(X86ISD::SETCC, dl, VT,
DAG.getConstant(X86CC, MVT::i8), EFLAGS);
}
DAG.getConstant(X86CC, MVT::i8), EFLAGS);
}
(COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
(f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
(COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
(f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
+def : Pat<(and VK1:$src1, VK1:$src2),
+ (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
+ (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
+
multiclass avx512_mask_binop_int<string IntName, string InstName> {
let Predicates = [HasAVX512] in
def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
multiclass avx512_mask_binop_int<string IntName, string InstName> {
let Predicates = [HasAVX512] in
def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")