};
static struct rt3261_init_reg init_list[] = {
- {RT3261_GEN_CTRL1 , 0x3701},//fa[12:13] = 1'b; fa[8~10]=1; fa[0]=1
+ {RT3261_GEN_CTRL1 , 0x3701},//fa[12:13] = 1'b; fa[8~10]=1; fa[0]=1
{RT3261_ADDA_CLK1 , 0x1114},//73[2] = 1'b
{RT3261_MICBIAS , 0x3030},//93[5:4] = 11'b
{RT3261_CLS_D_OUT , 0xa000},//8d[11] = 0'b
} else {
hp_amp_power_count--;
if(hp_amp_power_count <= 0) {
- rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
+ //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
snd_soc_update_bits(codec, RT3261_DEPOP_M1,
RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
msleep(30);
#if 0
- rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
+ //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
snd_soc_update_bits(codec, RT3261_DEPOP_M1,
RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
snd_soc_update_bits(codec, RT3261_DEPOP_M1,
RT3261_HP_CB_MASK, RT3261_HP_CB_PD);
msleep(30);
- rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
+ //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
0);
char *cookie_pot;
char *p;
int reg;
+ int i;
int value;
cookie_pot = (char *)vmalloc( len );
}
break;
case 'a':
- printk("Dump reg \n");
+ printk("Dump rt3261 dsp reg \n");
- for(reg = 0; reg < 0x6e; reg+=2)
+ for (i = 0; i < 0xb4; i++)
{
- value = rt3261_read(rt3261_codec,reg);
- printk("rt3261_read:0x%04x = 0x%04x\n",reg,value);
+ value = rt3261_index_read(rt3261_codec, i);
+ printk("rt3261_index_read:0x%04x = 0x%04x\n",i,value);
}
break;