V_DITHER_DOWN_SEL(0) |
V_DITHER_DOWN_MODE(0);
break;
+ case OUT_YUV_422:
+ face = OUT_YUV_422;
+ val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
+ V_PRE_DITHER_DOWN_EN(1) |
+ V_DITHER_DOWN_SEL(0) |
+ V_DITHER_DOWN_MODE(0);
+ break;
+ case OUT_YUV_422_10BIT:
+ face = OUT_YUV_422;
+ val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
+ V_PRE_DITHER_DOWN_EN(0) |
+ V_DITHER_DOWN_SEL(0) |
+ V_DITHER_DOWN_MODE(0);
+ break;
case OUT_P101010:
face = OUT_P101010;
val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
/*hsync vsync den dclk polo,dither */
vop_msk_reg(vop_dev, DSP_CTRL1, val);
break;
+ case SCREEN_DP:
+ dclk_ddr = 0;
+ if ((VOP_CHIP(vop_dev) == VOP_RK3399) &&
+ ((screen->face == OUT_P888) ||
+ (screen->face == OUT_P101010))) {
+ if (vop_dev->id == 0)
+ face = OUT_P101010;
+ else
+ face = OUT_P888;
+ }
+ val = V_DP_OUT_EN(1);
+ vop_msk_reg(vop_dev, SYS_CTRL, val);
+ val = V_DP_HSYNC_POL(screen->pin_hsync) |
+ V_DP_VSYNC_POL(screen->pin_vsync) |
+ V_DP_DEN_POL(screen->pin_den) |
+ V_DP_DCLK_POL(screen->pin_dclk);
+ /*hsync vsync den dclk polo,dither */
+ vop_msk_reg(vop_dev, DSP_CTRL1, val);
+ break;
default:
dev_err(vop_dev->dev, "un supported interface[%d]!\n",
screen->type);
#define V_EDP_OUT_EN(x) VAL_MASK(x, 1, 14)
#define V_MIPI_OUT_EN(x) VAL_MASK(x, 1, 15)
#define V_OVERLAY_MODE(x) VAL_MASK(x, 1, 16)
+/* rk3399 only*/
+#define V_DP_OUT_EN(x) VAL_MASK(x, 1, 11)
/* rk322x only */
#define V_FS_SAME_ADDR_MASK_EN(x) VAL_MASK(x, 1, 17)
#define V_POST_LB_MODE(x) VAL_MASK(x, 1, 18)
#define V_MIPI_VSYNC_POL(x) VAL_MASK(x, 1, 29)
#define V_MIPI_DEN_POL(x) VAL_MASK(x, 1, 30)
#define V_MIPI_DCLK_POL(x) VAL_MASK(x, 1, 31)
+/* rk3399 only*/
+#define V_DP_HSYNC_POL(x) VAL_MASK(x, 1, 16)
+#define V_DP_VSYNC_POL(x) VAL_MASK(x, 1, 17)
+#define V_DP_DEN_POL(x) VAL_MASK(x, 1, 18)
+#define V_DP_DCLK_POL(x) VAL_MASK(x, 1, 19)
#define DSP_BG 0x00000018
#define V_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0)
#define V_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10)