}
}
EXPORT_SYMBOL(rk2818_mux_api_set);
+
+unsigned int rk2818_mux_api_get(char *name)
+{
+ int i;
+ for(i=0;i<ARRAY_SIZE(rk2818_muxs);i++)
+ {
+ //if(rockchip_muxs[i].name == cfg->name)
+ if (!strcmp(rk2818_muxs[i].name, name))
+ {
+ return rk2818_muxs[i].mode;
+ }
+ }
+ return 0xff;
+}
+EXPORT_SYMBOL(rk2818_mux_api_get);
+
int err = 0;
pNANDC pRK28NC;
u_char maf_id,dev_id,ext_id3,ext_id4;
-
+ u32 iomux_mode0,iomux_mode1,iomux_mode2,iomux_mode3,iomux_mode4;
+ struct nand_chip *chip;
+
#ifdef CONFIG_MTD_PARTITIONS
struct mtd_partition *partitions = NULL;
int num_partitions = 0;
this->options |= NAND_BUSWIDTH_16;
this->ecc.layout = &nand_hw_eccoob_16;
}
-
+ //±£³ÖIO MUXÔʼֵ
+ iomux_mode0=rk2818_mux_api_get(GPIOA5_FLASHCS1_SEL_NAME);
+ iomux_mode1=rk2818_mux_api_get(GPIOA6_FLASHCS2_SEL_NAME);
+ iomux_mode2=rk2818_mux_api_get(GPIOA7_FLASHCS3_SEL_NAME);
+ iomux_mode3=rk2818_mux_api_get(GPIOE_SPI1_FLASH_SEL1_NAME);
+ iomux_mode4=rk2818_mux_api_get(GPIOE_SPI1_FLASH_SEL_NAME);
// iomux flash cs1~cs7
rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1);
rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2);
goto outscan;
}
+ //¸ù¾ÝƬѡÇé¿ö»Ö¸´IO MUXÔʼֵ
+ chip = mtd->priv;
+ switch(chip->numchips)
+ {
+ case 1:
+ rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, iomux_mode0);
+ case 2:
+ rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, iomux_mode1);
+ case 3:
+ rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, iomux_mode2);
+ case 4:
+ rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, iomux_mode3);
+ case 5:
+ case 6:
+ rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, iomux_mode4);
+ case 7:
+ case 8:
+ break;
+ default:
+ DEBUG(MTD_DEBUG_LEVEL0, "RK2818 NAND: numchips error!!!\n");
+ }
#if 0
// rk281x dma mode bch must (1k data + 32 oob) bytes align , so cheat system writesize =1024,oobsize=32
mtd->writesize = 1024;