MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.isDef())
continue;
+ // Ignore dead implicit defs.
+ if (MO.isImplicit() && MO.isDead())
+ continue;
unsigned Reg = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(Reg))
continue;
const MachineOperand &MO = Def->getOperand(OpIdx);
if (!MO.isReg() || !MO.getReg())
continue;
+ // Ignore dead implicit defs.
+ if (MO.isImplicit() && MO.isDead())
+ continue;
assert(!MO.isDef() && "We should have skipped all the definitions by now");
if (SrcIdx != EndOpIdx)
// Multiple sources?
%w = shl i64 %y, 32
ret i64 %w
}
+
+; CHECK-LABEL: bitcast_i32_to_float:
+; CHECK: f32.reinterpret/i32 $push0=, $0{{$}}
+define float @bitcast_i32_to_float(i32 %a) {
+ %t = bitcast i32 %a to float
+ ret float %t
+}
+
+; CHECK-LABEL: bitcast_float_to_i32:
+; CHECK: i32.reinterpret/f32 $push0=, $0{{$}}
+define i32 @bitcast_float_to_i32(float %a) {
+ %t = bitcast float %a to i32
+ ret i32 %t
+}
+
+; CHECK-LABEL: bitcast_i64_to_double:
+; CHECK: f64.reinterpret/i64 $push0=, $0{{$}}
+define double @bitcast_i64_to_double(i64 %a) {
+ %t = bitcast i64 %a to double
+ ret double %t
+}
+
+; CHECK-LABEL: bitcast_double_to_i64:
+; CHECK: i64.reinterpret/f64 $push0=, $0{{$}}
+define i64 @bitcast_double_to_i64(double %a) {
+ %t = bitcast double %a to i64
+ ret i64 %t
+}