#endif
}
+ int __sramdata gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
+
+void __sramfunc rk30_pwm_logic_suspend_voltage(void)
+{
+#ifdef CONFIG_RK30_PWM_REGULATOR
+
+// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
+ sram_udelay(10000);
+ gpio0d7_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
+ gpio0d7_do = grf_readl(GRF_GPIO0H_DO);
+ gpio0d7_dir = grf_readl(GRF_GPIO0H_DIR);
+ gpio0d7_en = grf_readl(GRF_GPIO0H_EN);
+
+ writel_relaxed((1<<30), GRF_GPIO0D_IOMUX);
+ grf_writel((1<<31)|(1<<15), GRF_GPIO0H_DIR);
+ grf_writel((1<<31)|(1<<15), GRF_GPIO0H_DO);
+ grf_writel((1<<31)|(1<<15), GRF_GPIO0H_EN);
+#endif
+}
+void __sramfunc rk30_pwm_logic_resume_voltage(void)
+{
+#ifdef CONFIG_RK30_PWM_REGULATOR
+ writel_relaxed((1<<30)|gpio0d7_iomux, GRF_GPIO0D_IOMUX);
+ grf_writel((1<<31)|gpio0d7_en, GRF_GPIO0H_EN);
+ grf_writel((1<<31)|gpio0d7_dir, GRF_GPIO0H_DIR);
+ grf_writel((1<<31)|gpio0d7_do, GRF_GPIO0H_DO);
+ sram_udelay(10000);
+
+#endif
+
+}
+extern void pwm_suspend_voltage(void);
+extern void pwm_resume_voltage(void);
+void rk30_pwm_suspend_voltage_set(void)
+{
+#ifdef CONFIG_RK30_PWM_REGULATOR
+ pwm_suspend_voltage();
+#endif
+}
+void rk30_pwm_resume_voltage_set(void)
+{
+#ifdef CONFIG_RK30_PWM_REGULATOR
+ pwm_resume_voltage();
+#endif
+}
+
#ifdef CONFIG_I2C2_RK30
static struct i2c_board_info __initdata i2c2_info[] = {
__weak void __sramfunc board_pmu_resume(void) {}
__weak void __sramfunc rk30_suspend_voltage_set(unsigned int vol){}
__weak void __sramfunc rk30_suspend_voltage_resume(unsigned int vol){}
+
+__weak void rk30_pwm_suspend_voltage_set(void){}
+__weak void rk30_pwm_resume_voltage_set(void){}
+
+__weak void __sramfunc rk30_pwm_logic_suspend_voltage(void){}
+__weak void __sramfunc rk30_pwm_logic_resume_voltage(void){}
+
static void __sramfunc rk30_sram_suspend(void)
{
u32 cru_clksel0_con;
ddr_suspend();
sram_printch('6');
rk30_suspend_voltage_set(1000000);
+ rk30_pwm_logic_suspend_voltage();
sram_printch('7');
| (1 << CLK_GATE_PCLK_GRF % 16)
| (1 << CLK_GATE_PCLK_PMU % 16)
, clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
+ gate_save_soc_clk(0 , clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_CLK_L2C % 16)
| (1 << CLK_GATE_ACLK_INTMEM0 % 16)
}
sram_printch('7');
+ rk30_pwm_logic_resume_voltage();
rk30_suspend_voltage_resume(1100000);
+
sram_printch('6');
ddr_resume();
sram_printch('5');
pmu_pwrdn_st = pmu_readl(PMU_PWRDN_ST);
rk30_pm_set_power_domain(pmu_pwrdn_st, false);
- #ifdef CONFIG_DDR_TEST
+#ifdef CONFIG_DDR_TEST
// memory tester
if (ddr_debug != 0)
ddr_testmode();
- #endif
+ #endif
sram_printch('1');
local_fiq_disable();
gate_save_soc_clk(0
| (1 << CLK_GATE_PEIRPH_SRC % 16)
| (1 << CLK_GATE_PCLK_PEIRPH % 16)
+ | (1 << CLK_GATE_ACLK_PEIRPH % 16)
, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
gate_save_soc_clk(0, clkgt_regs[3], CRU_CLKGATES_CON(3), 0xff9f);
gate_save_soc_clk(0
| (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
, clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
gate_save_soc_clk(0, clkgt_regs[6], CRU_CLKGATES_CON(6), 0xffff);
- gate_save_soc_clk(0, clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
+ gate_save_soc_clk(0
+ |(1 << CLK_GATE_PCLK_PWM23%16)
+ , clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
gate_save_soc_clk(0 , clkgt_regs[8], CRU_CLKGATES_CON(8), 0x01ff);
gate_save_soc_clk(0
| (1 << CLK_GATE_CLK_L2C % 16)
cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_DN, PLL_CONS(APLL_ID, 3));
sram_printch('3');
+ rk30_pwm_suspend_voltage_set();
board_gpio_suspend();
sram_printch('4');
board_gpio_resume();
-
+ rk30_pwm_resume_voltage_set();
sram_printch('3');
//apll