rk3036:clk:rename clk_core_pre to clk_core

diff --git a/arch/arm/boot/dts/rk3036-clocks.dtsi b/arch/arm/boot/dts/rk3036-clocks.dtsi
index aa9c1675b95762e604b1c4861bb35eefb66b4357..9b48f81ee543cef3f0d9c09d183fb11360a06ad1 100755 (executable)
--- a/arch/arm/boot/dts/rk3036-clocks.dtsi
+++ b/arch/arm/boot/dts/rk3036-clocks.dtsi
@@ -138,7 +138,7 @@
                                        status-reg = <0x0014 10>;
                                        clocks = <&xin24m>;
                                        clock-output-names = "clk_dpll";
-                                       rockchip,pll-type = <CLK_PLL_3188PLUS>;
+                                       rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
                                        #clock-cells = <0>;
                                };
 
@@ -169,11 +169,11 @@
                                        #address-cells = <1>;
                                        #size-cells = <1>;
 
-                                       clk_core_pre_div: clk_core_pre_div {
+                                       clk_core_div: clk_core_div {
                                                compatible = "rockchip,rk3188-div-con";
                                                rockchip,bits = <0 5>;
-                                               clocks = <&clk_core_pre>;
-                                               clock-output-names = "clk_core_pre";
+                                               clocks = <&clk_core>;
+                                               clock-output-names = "clk_core";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
@@ -183,11 +183,11 @@
 
                                        /* reg[6:5]: reserved */
 
-                                       clk_core_pre: clk_core_pre_mux {
+                                       clk_core: clk_core_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <7 1>;
                                                clocks = <&clk_apll>, <&clk_gates0 6>;
-                                               clock-output-names = "clk_core_pre";
+                                               clock-output-names = "clk_core";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
                                        };
@@ -226,7 +226,7 @@
                                        pclk_dbg_div:  pclk_dbg_div {
                                                compatible = "rockchip,rk3188-div-con";
                                                rockchip,bits = <0 4>;
-                                               clocks = <&clk_core_pre>;
+                                               clocks = <&clk_core>;
                                                clock-output-names = "pclk_dbg";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
@@ -236,7 +236,7 @@
                                        aclk_core_pre: aclk_core_pre_div {
                                                compatible = "rockchip,rk3188-div-con";
                                                rockchip,bits = <4 3>;
-                                               clocks = <&clk_core_pre>;
+                                               clocks = <&clk_core>;
                                                clock-output-names = "aclk_core_pre";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
@@ -1139,11 +1139,11 @@
                                        compatible = "rockchip,rk3188-gate-clk";
                                        reg = <0x00d0 0x4>;
                                        clocks =
-                                               <&clk_core_pre>,                <&clk_gpll>,
+                                               <&clk_core>,            <&clk_gpll>,
                                                <&clk_dpll>,    <&aclk_cpu_pre>,
 
                                                <&aclk_cpu_pre>,        <&aclk_cpu_pre>,
-                                               <&clk_gpll>,            <&clk_core_pre>,
+                                               <&clk_gpll>,            <&clk_core>,
 
                                                <&clk_gpll>,    <&clk_i2s_pll>,
                                                <&i2s_frac>,    <&hclk_vio_pre>,

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index d24d0845aaa9247cc4bd5b3108d31bf183aa1103..cf7f304c63cdcb5b572d50d9165c3a9b863b404b 100755 (executable)
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -185,13 +185,13 @@
        clocks-init{
                compatible = "rockchip,clocks-init";
                rockchip,clocks-init-parent =
-                       <&clk_core_pre &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
+                       <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
                        <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,  
                        <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
                        <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
                        <&clk_mac_pll &clk_apll>;
                rockchip,clocks-init-rate =
-                       <&clk_core_pre 816000000>, <&clk_gpll 594000000>,
+                       <&clk_core 816000000>, <&clk_gpll 594000000>,
                        <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,    
                        <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
                        <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,

diff --git a/drivers/clk/rockchip/clk-pll.h b/drivers/clk/rockchip/clk-pll.h
index c3605aa27e2276a0d94daccef308ee026101747c..df41b57644fe36bb33e20fbd007220d7513f8579 100755 (executable)
--- a/drivers/clk/rockchip/clk-pll.h
+++ b/drivers/clk/rockchip/clk-pll.h
@@ -258,22 +258,6 @@
 }
 /***************************RK3036 PLL**************************************/
 #define LPJ_24M        (CLK_LOOPS_JIFFY_REF * 24) / CLK_LOOPS_RATE_REF
-/*****cru reg offset*****/
-#define RK3036_CRU_CLKSEL_CON          0x44
-#define RK3036_CRU_CLKGATE_CON         0xd0
-#define RK3036_CRU_GLB_SRST_FST        0x100
-#define RK3036_CRU_GLB_SRST_SND        0x104
-#define RK3036_CRU_SOFTRST_CON         0x110
-
-#define RK3036_CRU_CLKSELS_CON_CNT     (35)
-#define RK3036_CRU_CLKSELS_CON(i)      (RK3036_CRU_CLKSEL_CON + ((i) * 4))
-
-#define RK3036_CRU_CLKGATES_CON_CNT    (10)
-#define RK3036_CRU_CLKGATES_CON(i)     (RK3036_CRU_CLKGATE_CON + ((i) * 4))
-
-#define RK3036_CRU_SOFTRSTS_CON_CNT    (9)
-#define RK3036_CRU_SOFTRSTS_CON(i)     (RK3036_CRU_SOFTRST_CON + ((i) * 4))
-
 /*PLL_CON 0,1,2*/
 #define RK3036_PLL_PWR_ON                      (0)
 #define RK3036_PLL_PWR_DN                      (1)

diff --git a/include/linux/rockchip/cru.h b/include/linux/rockchip/cru.h
index 2a903489fcb0f454e581582271d324ac888c230e..2205d5b6c20a364f4cc4d8316548a3780a9e19e0 100755 (executable)
--- a/include/linux/rockchip/cru.h
+++ b/include/linux/rockchip/cru.h
@@ -149,5 +149,16 @@ static inline void rk3288_cru_set_soft_reset(u32 idx, bool on)
 #define RK3036_CRU_RST_ST 0x00160
 #define RK3036_CRU_PLL_MASK_CON 0x001f0
 
+#define RK3036_CRU_CLKSEL_CON          0x44
+#define RK3036_CRU_CLKGATE_CON         0xd0
+
+#define RK3036_CRU_CLKSELS_CON_CNT     (35)
+#define RK3036_CRU_CLKSELS_CON(i)      (RK3036_CRU_CLKSEL_CON + ((i) * 4))
+
+#define RK3036_CRU_CLKGATES_CON_CNT    (10)
+#define RK3036_CRU_CLKGATES_CON(i)     (RK3036_CRU_CLKGATE_CON + ((i) * 4))
+
+#define RK3036_CRU_SOFTRSTS_CON_CNT    (9)
+#define RK3036_CRU_SOFTRSTS_CON(i)     (RK3036_CRU_SOFTRST_CON + ((i) * 4))
 
 #endif