Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39843 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index 11251e92581c93f3f3d6e9f632c49f1f3ec9b428..8e2f4444b858414a538e9960c572c2c6547f519f 100644 (file)
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -26,9 +26,9 @@ class Rf<bits<5> num, string n> : SparcReg<n> {
   let Num = num;
 }
 // Rd - Slots in the FP register file for 64-bit floating-point values.
-class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
+class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
   let Num = num;
-  let Aliases = aliases;
+  let SubRegs = subregs;
 }
 
 // Integer registers