Now that register classes have names, include the name in debug output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68786 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index 4ad36dac79a7ab4c1324c47e2dfb1538def24c5b..abeb7f4dbf7ce4436f422a80d3f6b97ef87b1365 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -268,9 +268,11 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
         cerr << "Op->Val = "; Op.getNode()->dump(DAG); cerr << "\n";
         cerr << "MI = "; MI->print(cerr);
         cerr << "VReg = " << VReg << "\n";
-        cerr << "VReg RegClass     size = " << VRC->getSize()
+        cerr << "VReg RegClass " << VRC->getName()
+             << "     size = " << VRC->getSize()
              << ", align = " << VRC->getAlignment() << "\n";
-        cerr << "Expected RegClass size = " << RC->getSize()
+        cerr << "Expected RegClass " << RC->getName()
+             << " size = " << RC->getSize()
              << ", align = " << RC->getAlignment() << "\n";
         cerr << "Fatal error, aborting.\n";
         abort();