git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119308
91177308-0d34-0410-b5e6-
96231b3b80d8
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const {
if (MO.isReg()) {
+ // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
+ // The GPR operand should come through here though.
assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
return PPCRegisterInfo::getRegisterNumbering(MO.getReg());