arm64: dts: rk3368: don't assign clock rates for display pll

NPLL is used for display pixelclock, assign clock rates would overlap
loader pll setting, cause display abnormal.

Change-Id: Iaf1094c43526c7ca7b364608fa7153d03f84326c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 19913eaa00e70f761201622f09c0b1f11e989563..c3a29e31c953e7092fedf012a6a82e9fe17edd39 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -1045,13 +1045,11 @@
                #reset-cells = <1>;
                assigned-clocks =
                        <&cru PLL_GPLL>, <&cru PLL_CPLL>,
-                       <&cru PLL_NPLL>,
                        <&cru ACLK_BUS>, <&cru ACLK_PERI>,
                        <&cru HCLK_BUS>, <&cru HCLK_PERI>,
                        <&cru PCLK_BUS>, <&cru PCLK_PERI>;
                assigned-clock-rates =
                        <576000000>, <400000000>,
-                       <1188000000>,
                        <300000000>, <300000000>,
                        <150000000>, <150000000>,
                        <75000000>, <75000000>;