static void __init machine_rk30_board_init(void)
{
- //avs_init();
+ avs_init();
gpio_request(POWER_ON_PIN, "poweronpin");
gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
clk_enable_nolock(&clk_hclk_emem_peri);
//clk_enable_nolock(&clk_hclk_mac);
- //clk_enable_nolock(&clk_nandc);
+ clk_enable_nolock(&clk_nandc);
clk_enable_nolock(&clk_hclk_usb_peri);
#if 0
clk_enable_nolock(&clk_hclk_otg0);
//RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
};\r
#endif\r
-//static struct avs_ctr_st rk30_avs_ctr;\r
+static struct avs_ctr_st rk30_avs_ctr;\r
\r
int rk3188_dvfs_init(void)\r
{\r
#ifndef NO_VOLT_DIFF\r
dvfs_clk_cpu = dvfs_get_dvfs_clk_byname("cpu");\r
#endif\r
- //avs_board_init(&rk30_avs_ctr);\r
+ avs_board_init(&rk30_avs_ctr);\r
return 0;\r
}\r
\r
\r
\r
/******************************rk30 avs**************************************************/\r
-\r
-#if 0\r
-\r
static void __iomem *rk30_nandc_base=NULL;\r
\r
#define nandc_readl(offset) readl_relaxed(rk30_nandc_base + offset)\r
nandc_writel(nanc_save_reg[0] | 0x1 << 14, 0);\r
nandc_writel(0x5, 0x130);\r
\r
- nandc_writel(3, 0x158);\r
- nandc_writel(1, 0x134);\r
+ nandc_writel(0x3, 0x158);\r
+ nandc_writel(0x21, 0x134);\r
\r
while(count--) {\r
paramet = nandc_readl(0x138);\r
.avs_init =rk30_avs_init,\r
.avs_get_val = rk30_get_avs_val,\r
};\r
-#endif\r
\r
\r
memset(&init_avs_paramet[0].is_set, 0, sizeof(init_avs_paramet));\r
if(avs_ctr_data&&avs_ctr_data->avs_init)\r
avs_ctr_data->avs_init();\r
- avs_init_val_get(0,1150000,"board_init");\r
+ //avs_init_val_get(0,1150000,"board_init");\r
}\r
static u8 rk_get_avs_val(void)\r
{\r
init_avs_paramet[index].vol = vol;\r
init_avs_paramet[index].s = s;\r
init_avs_paramet[index].is_set++;\r
+ printk("DVFS MSG:\tAVS Value(index=%d): ", index);\r
for(i = 0; i < init_avs_times; i++) {\r
init_avs_paramet[index].paramet[i] = rk_get_avs_val();\r
mdelay(1);\r
+ printk("%d ", init_avs_paramet[index].paramet[i]);\r
}\r
+ printk("\n");\r
}\r
int avs_set_scal_val(u8 avs_base)\r
{\r