x86: Add new Intel CPU cache size descriptors

commit 85160b92fbd35321104819283c91bfed2b553e3c upstream.

The latest rev of Intel doc AP-485 details new cache descriptors
that we don't yet support. 12MB, 18MB and 24MB 24-way assoc L3
caches.

Signed-off-by: Dave Jones <davej@redhat.com>
LKML-Reference: <20091110184924.GA20337@redhat.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 804c40e2bc3e1fd588f08f50db90dc83e02ae1b4..14103924b6272548a635364af5816e193bd2be9b 100644 (file)
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -102,6 +102,9 @@ static const struct _cache_table __cpuinitconst cache_table[] =
        { 0xe2, LVL_3,    2048 },       /* 16-way set assoc, 64 byte line size */
        { 0xe3, LVL_3,    4096 },       /* 16-way set assoc, 64 byte line size */
        { 0xe4, LVL_3,    8192 },       /* 16-way set assoc, 64 byte line size */
+       { 0xea, LVL_3,    12288 },      /* 24-way set assoc, 64 byte line size */
+       { 0xeb, LVL_3,    18432 },      /* 24-way set assoc, 64 byte line size */
+       { 0xec, LVL_3,    24576 },      /* 24-way set assoc, 64 byte line size */
        { 0x00, 0, 0}
 };