The Mips standalone assembler aliased instruction support.

The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.

These changes are in the instruction td file.

Test cases included

Contributer: Vladimir Medic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 6202babc22599181a9390277a260c8468f4dcf93..6b6005fd759f40986168450f892dfa0dec3d1347 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1079,6 +1079,26 @@ def RDHWR : ReadHardware<CPURegs, HWRegs>;
 def EXT : ExtBase<0, "ext", CPURegs>;
 def INS : InsBase<4, "ins", CPURegs>;
 
+//===----------------------------------------------------------------------===//
+// Instruction aliases
+//===----------------------------------------------------------------------===//
+def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
+def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
+def : InstAlias<"addu $rs,$rt,$imm",
+                (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
+def : InstAlias<"add $rs,$rt,$imm",
+                (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
+def : InstAlias<"and $rs,$rt,$imm",
+                (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
+def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
+def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
+def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
+def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
+def : InstAlias<"slt $rs,$rt,$imm",
+                (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
+def : InstAlias<"xor $rs,$rt,$imm",
+                (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//

diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s
index fb816e51e6e847dcb0f73937e05bef7cd1808c88..2997782cd01b4fdaeee956757eddba7570c29b27 100644 (file)
--- a/test/MC/Mips/mips-alu-instructions.s
+++ b/test/MC/Mips/mips-alu-instructions.s
@@ -7,6 +7,7 @@
 #------------------------------------------------------------------------------
 # CHECK:  and    $9, $6, $7      # encoding: [0x24,0x48,0xc7,0x00]
 # CHECK:  andi   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x30]
+# CHECK:  andi   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x30]
 # CHECK:  clo    $6, $7          # encoding: [0x21,0x30,0xe6,0x70]
 # CHECK:  clz    $6, $7          # encoding: [0x20,0x30,0xe6,0x70]
 # CHECK:  ins    $19, $9, 6, 7   # encoding: [0x84,0x61,0x33,0x7d]
@@ -19,6 +20,7 @@
 # CHECK:  sllv   $2, $3, $5      # encoding: [0x04,0x10,0xa3,0x00]
 # CHECK:  slt    $3, $3, $5      # encoding: [0x2a,0x18,0x65,0x00]
 # CHECK:  slti   $3, $3, 103     # encoding: [0x67,0x00,0x63,0x28]
+# CHECK:  slti   $3, $3, 103     # encoding: [0x67,0x00,0x63,0x28]
 # CHECK:  sltiu  $3, $3, 103     # encoding: [0x67,0x00,0x63,0x2c]
 # CHECK:  sltu   $3, $3, $5      # encoding: [0x2b,0x18,0x65,0x00]
 # CHECK:  sra    $4, $3, 7       # encoding: [0xc3,0x21,0x03,0x00]
@@ -26,9 +28,12 @@
 # CHECK:  srl    $4, $3, 7       # encoding: [0xc2,0x21,0x03,0x00]
 # CHECK:  srlv   $2, $3, $5      # encoding: [0x06,0x10,0xa3,0x00]
 # CHECK:  xor    $3, $3, $5      # encoding: [0x26,0x18,0x65,0x00]
+# CHECK:  xori    $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x38]
 # CHECK:  xori   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x38]
 # CHECK:  wsbh   $6, $7          # encoding: [0xa0,0x30,0x07,0x7c]
+# CHECK:  nor    $7, $8, $zero   # encoding: [0x27,0x38,0x00,0x01]
      and    $9,  $6, $7
+     and    $9,  $6, 17767
      andi   $9,  $6, 17767
      clo    $6,  $7
      clz    $6,  $7
@@ -41,6 +46,7 @@
      sll    $4,  $3, 7
      sllv   $2,  $3, $5
      slt    $3,  $3, $5
+     slt    $3,  $3, 103
      slti   $3,  $3, 103
      sltiu  $3,  $3, 103
      sltu   $3,  $3, $5
@@ -49,8 +55,11 @@
      srl    $4,  $3, 7
      srlv   $2,  $3, $5
      xor    $3,  $3, $5
+     xor    $9,  $6, 17767
      xori   $9,  $6, 17767
      wsbh   $6,  $7
+     not    $7  ,$8
+
 #------------------------------------------------------------------------------
 # Arithmetic instructions
 #------------------------------------------------------------------------------
@@ -58,6 +67,8 @@
 # CHECK:  add    $9, $6, $7      # encoding: [0x20,0x48,0xc7,0x00]
 # CHECK:  addi   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x20]
 # CHECK:  addiu  $9, $6, -15001  # encoding: [0x67,0xc5,0xc9,0x24]
+# CHECK:  addi   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x20]
+# CHECK:  addiu  $9, $6, -15001  # encoding: [0x67,0xc5,0xc9,0x24]
 # CHECK:  addu   $9, $6, $7      # encoding: [0x21,0x48,0xc7,0x00]
 # CHECK:  madd   $6, $7          # encoding: [0x00,0x00,0xc7,0x70]
 # CHECK:  maddu  $6, $7          # encoding: [0x01,0x00,0xc7,0x70]
@@ -67,7 +78,12 @@
 # CHECK:  multu  $3, $5          # encoding: [0x19,0x00,0x65,0x00]
 # CHECK:  sub    $9, $6, $7      # encoding: [0x22,0x48,0xc7,0x00]
 # CHECK:  subu   $4, $3, $5      # encoding: [0x23,0x20,0x65,0x00]
+# CHECK:  sub     $6, $zero, $7  # encoding: [0x22,0x30,0x07,0x00]
+# CHECK:  subu    $6, $zero, $7  # encoding: [0x23,0x30,0x07,0x00]
+# CHECK:  add     $7, $8, $zero  # encoding: [0x20,0x38,0x00,0x01]
     add    $9,$6,$7
+    add    $9,$6,17767
+    addu   $9,$6,-15001
     addi   $9,$6,17767
     addiu  $9,$6,-15001
     addu   $9,$6,$7
@@ -79,3 +95,6 @@
     multu  $3,$5
     sub    $9,$6,$7
     subu   $4,$3,$5
+    neg    $6,$7
+    negu   $6,$7
+    move   $7,$8

diff --git a/test/MC/Mips/mips-jump-instructions.s b/test/MC/Mips/mips-jump-instructions.s
index 5188751fe85757a6915667def7e534e1064bb418..998be418d2049cf4a836d7e76dafda8fce49a37d 100644 (file)
--- a/test/MC/Mips/mips-jump-instructions.s
+++ b/test/MC/Mips/mips-jump-instructions.s
@@ -22,6 +22,8 @@
 # CHECK:   blez $6, 1332          # encoding: [0x34,0x05,0xc0,0x18]
 # CHECK:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 # CHECK:   bne $9, $6, 1332       # encoding: [0x34,0x05,0x26,0x15]
+# CHECK:   nop                    # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:   bal     1332           # encoding: [0x34,0x05,0x00,0x04]
 # CHECK:   nop                    # encoding: [0x00,0x00,0x00,0x00]
          b 1332
          nop
@@ -41,6 +43,8 @@
          nop
          bne $9,$6,1332
          nop
+         bal 1332
+         nop
 
 end_of_code:
 #------------------------------------------------------------------------------
@@ -52,6 +56,8 @@ end_of_code:
 # CHECK:   nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK:   jalr $6              # encoding: [0x09,0xf8,0xc0,0x00]
 # CHECK:   nop                  # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:   jr $7                # encoding: [0x08,0x00,0xe0,0x00]
+# CHECK:   nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK:   jr $7                # encoding: [0x08,0x00,0xe0,0x00]
 
 
@@ -62,3 +68,5 @@ end_of_code:
    jalr $6
    nop
    jr $7
+   nop
+   j $7