Merge branch 'for-tony' of git://gitorious.org/usb/usb into omap-for-linus
authorTony Lindgren <tony@atomide.com>
Tue, 22 Feb 2011 18:54:12 +0000 (10:54 -0800)
committerTony Lindgren <tony@atomide.com>
Tue, 22 Feb 2011 18:54:12 +0000 (10:54 -0800)
Conflicts:
arch/arm/mach-omap2/omap_hwmod_2430_data.c
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

1  2 
arch/arm/mach-omap2/Makefile
arch/arm/mach-omap2/board-4430sdp.c
arch/arm/mach-omap2/board-am3517evm.c
arch/arm/mach-omap2/omap_hwmod_2430_data.c
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

Simple merge
index 12d99e582cd651864b289ed70df1131191f5a488,674c183f8130952b25f732cc283700d1cad97eb8..bf8268438d006d257746f93212d420b1779d995d
@@@ -248,18 -247,9 +247,8 @@@ static void __init omap_4430sdp_init_ea
  #ifdef CONFIG_OMAP_32K_TIMER
        omap2_gp_clockevent_set_gptimer(1);
  #endif
 -      gic_init_irq();
  }
  
- static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-       .port_mode[0]   = EHCI_HCD_OMAP_MODE_PHY,
-       .port_mode[1]   = EHCI_HCD_OMAP_MODE_UNKNOWN,
-       .port_mode[2]   = EHCI_HCD_OMAP_MODE_UNKNOWN,
-       .phy_reset      = false,
-       .reset_gpio_port[0]  = -EINVAL,
-       .reset_gpio_port[1]  = -EINVAL,
-       .reset_gpio_port[2]  = -EINVAL,
- };
  static struct omap_musb_board_data musb_board_data = {
        .interface_type         = MUSB_INTERFACE_UTMI,
        .mode                   = MUSB_OTG,
Simple merge
index 60fe4aac1f501f725c03617fe9c1e6d765658fc4,76bbf8a4703116dcac840fcdf17a3cef004a0f0d..7ba688a1c84091be89ea7ff319928d8f658109db
@@@ -977,162 -958,62 +1016,220 @@@ static struct omap_hwmod omap2430_dma_s
        .flags          = HWMOD_NO_IDLEST,
  };
  
 +/*
 + * 'mcspi' class
 + * multichannel serial port interface (mcspi) / master/slave synchronous serial
 + * bus
 + */
 +
 +static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
 +      .rev_offs       = 0x0000,
 +      .sysc_offs      = 0x0010,
 +      .syss_offs      = 0x0014,
 +      .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 +                              SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 +                              SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 +      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +      .sysc_fields    = &omap_hwmod_sysc_type1,
 +};
 +
 +static struct omap_hwmod_class omap2430_mcspi_class = {
 +      .name = "mcspi",
 +      .sysc = &omap2430_mcspi_sysc,
 +      .rev = OMAP2_MCSPI_REV,
 +};
 +
 +/* mcspi1 */
 +static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
 +      { .irq = 65 },
 +};
 +
 +static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
 +      { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
 +      { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
 +      { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
 +      { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
 +      { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
 +      { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
 +      { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
 +      { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
 +};
 +
 +static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
 +      &omap2430_l4_core__mcspi1,
 +};
 +
 +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 +      .num_chipselect = 4,
 +};
 +
 +static struct omap_hwmod omap2430_mcspi1_hwmod = {
 +      .name           = "mcspi1_hwmod",
 +      .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
 +      .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
 +      .main_clk       = "mcspi1_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 +              },
 +      },
 +      .slaves         = omap2430_mcspi1_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
 +      .class          = &omap2430_mcspi_class,
 +      .dev_attr       = &omap_mcspi1_dev_attr,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 +};
 +
 +/* mcspi2 */
 +static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
 +      { .irq = 66 },
 +};
 +
 +static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
 +      { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
 +      { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
 +      { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
 +      { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
 +};
 +
 +static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
 +      &omap2430_l4_core__mcspi2,
 +};
 +
 +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 +      .num_chipselect = 2,
 +};
 +
 +static struct omap_hwmod omap2430_mcspi2_hwmod = {
 +      .name           = "mcspi2_hwmod",
 +      .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
 +      .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
 +      .main_clk       = "mcspi2_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 +              },
 +      },
 +      .slaves         = omap2430_mcspi2_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
 +      .class          = &omap2430_mcspi_class,
 +      .dev_attr       = &omap_mcspi2_dev_attr,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 +};
 +
 +/* mcspi3 */
 +static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
 +      { .irq = 91 },
 +};
 +
 +static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
 +      { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
 +      { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
 +      { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
 +      { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
 +};
 +
 +static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
 +      &omap2430_l4_core__mcspi3,
 +};
 +
 +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
 +      .num_chipselect = 2,
 +};
 +
 +static struct omap_hwmod omap2430_mcspi3_hwmod = {
 +      .name           = "mcspi3_hwmod",
 +      .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
 +      .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
 +      .main_clk       = "mcspi3_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 2,
 +                      .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
 +                      .idlest_reg_id = 2,
 +                      .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
 +              },
 +      },
 +      .slaves         = omap2430_mcspi3_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
 +      .class          = &omap2430_mcspi_class,
 +      .dev_attr       = &omap_mcspi3_dev_attr,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 +};
 +
+ /*
+  * usbhsotg
+  */
+ static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
+       .rev_offs       = 0x0400,
+       .sysc_offs      = 0x0404,
+       .syss_offs      = 0x0408,
+       .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                         SYSC_HAS_AUTOIDLE),
+       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                         MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+       .sysc_fields    = &omap_hwmod_sysc_type1,
+ };
+ static struct omap_hwmod_class usbotg_class = {
+       .name = "usbotg",
+       .sysc = &omap2430_usbhsotg_sysc,
+ };
+ /* usb_otg_hs */
+ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
+       { .name = "mc", .irq = 92 },
+       { .name = "dma", .irq = 93 },
+ };
+ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
+       .name           = "usb_otg_hs",
+       .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
+       .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
+       .main_clk       = "usbhs_ick",
+       .prcm           = {
+               .omap2 = {
+                       .prcm_reg_id = 1,
+                       .module_bit = OMAP2430_EN_USBHS_MASK,
+                       .module_offs = CORE_MOD,
+                       .idlest_reg_id = 1,
+                       .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
+               },
+       },
+       .masters        = omap2430_usbhsotg_masters,
+       .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
+       .slaves         = omap2430_usbhsotg_slaves,
+       .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
+       .class          = &usbotg_class,
+       /*
+        * Erratum ID: i479  idle_req / idle_ack mechanism potentially
+        * broken when autoidle is enabled
+        * workaround is to disable the autoidle bit at module level.
+        */
+       .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+                               | HWMOD_SWSUP_MSTANDBY,
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
++
++
  static __initdata struct omap_hwmod *omap2430_hwmods[] = {
        &omap2430_l3_main_hwmod,
        &omap2430_l4_core_hwmod,
        /* dma_system class*/
        &omap2430_dma_system_hwmod,
  
 +      /* mcspi class */
 +      &omap2430_mcspi1_hwmod,
 +      &omap2430_mcspi2_hwmod,
 +      &omap2430_mcspi3_hwmod,
++
+       /* usbotg class*/
+       &omap2430_usbhsotg_hwmod,
++
        NULL,
  };
  
index 800eda4adb547e2ebde3be197d6e695d4f8c79ac,b4cd8ddf963ed295e2e8e703abbf4cc9b3a6736f..879f55f272e2518ce2e4905d6f46b7e2926051bd
@@@ -56,11 -56,9 +57,12 @@@ static struct omap_hwmod omap3xxx_gpio5
  static struct omap_hwmod omap3xxx_gpio6_hwmod;
  static struct omap_hwmod omap34xx_sr1_hwmod;
  static struct omap_hwmod omap34xx_sr2_hwmod;
 +static struct omap_hwmod omap34xx_mcspi1;
 +static struct omap_hwmod omap34xx_mcspi2;
 +static struct omap_hwmod omap34xx_mcspi3;
 +static struct omap_hwmod omap34xx_mcspi4;
+ static struct omap_hwmod am35xx_usbhsotg_hwmod;
  
 -
  static struct omap_hwmod omap3xxx_dma_system_hwmod;
  
  /* L3 -> L4_CORE interface */
@@@ -1361,275 -1430,91 +1434,360 @@@ static struct omap_hwmod omap36xx_sr2_h
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
  };
  
 -
 +/* l4 core -> mcspi1 interface */
 +static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
 +      {
 +              .pa_start       = 0x48098000,
 +              .pa_end         = 0x480980ff,
 +              .flags          = ADDR_TYPE_RT,
 +      },
 +};
 +
 +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
 +      .master         = &omap3xxx_l4_core_hwmod,
 +      .slave          = &omap34xx_mcspi1,
 +      .clk            = "mcspi1_ick",
 +      .addr           = omap34xx_mcspi1_addr_space,
 +      .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l4 core -> mcspi2 interface */
 +static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
 +      {
 +              .pa_start       = 0x4809a000,
 +              .pa_end         = 0x4809a0ff,
 +              .flags          = ADDR_TYPE_RT,
 +      },
 +};
 +
 +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
 +      .master         = &omap3xxx_l4_core_hwmod,
 +      .slave          = &omap34xx_mcspi2,
 +      .clk            = "mcspi2_ick",
 +      .addr           = omap34xx_mcspi2_addr_space,
 +      .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l4 core -> mcspi3 interface */
 +static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
 +      {
 +              .pa_start       = 0x480b8000,
 +              .pa_end         = 0x480b80ff,
 +              .flags          = ADDR_TYPE_RT,
 +      },
 +};
 +
 +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
 +      .master         = &omap3xxx_l4_core_hwmod,
 +      .slave          = &omap34xx_mcspi3,
 +      .clk            = "mcspi3_ick",
 +      .addr           = omap34xx_mcspi3_addr_space,
 +      .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l4 core -> mcspi4 interface */
 +static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
 +      {
 +              .pa_start       = 0x480ba000,
 +              .pa_end         = 0x480ba0ff,
 +              .flags          = ADDR_TYPE_RT,
 +      },
 +};
 +
 +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
 +      .master         = &omap3xxx_l4_core_hwmod,
 +      .slave          = &omap34xx_mcspi4,
 +      .clk            = "mcspi4_ick",
 +      .addr           = omap34xx_mcspi4_addr_space,
 +      .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/*
 + * 'mcspi' class
 + * multichannel serial port interface (mcspi) / master/slave synchronous serial
 + * bus
 + */
 +
 +static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
 +      .rev_offs       = 0x0000,
 +      .sysc_offs      = 0x0010,
 +      .syss_offs      = 0x0014,
 +      .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 +                              SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 +                              SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 +      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +      .sysc_fields    = &omap_hwmod_sysc_type1,
 +};
 +
 +static struct omap_hwmod_class omap34xx_mcspi_class = {
 +      .name = "mcspi",
 +      .sysc = &omap34xx_mcspi_sysc,
 +      .rev = OMAP3_MCSPI_REV,
 +};
 +
 +/* mcspi1 */
 +static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
 +      { .name = "irq", .irq = 65 },
 +};
 +
 +static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
 +      { .name = "tx0", .dma_req = 35 },
 +      { .name = "rx0", .dma_req = 36 },
 +      { .name = "tx1", .dma_req = 37 },
 +      { .name = "rx1", .dma_req = 38 },
 +      { .name = "tx2", .dma_req = 39 },
 +      { .name = "rx2", .dma_req = 40 },
 +      { .name = "tx3", .dma_req = 41 },
 +      { .name = "rx3", .dma_req = 42 },
 +};
 +
 +static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
 +      &omap34xx_l4_core__mcspi1,
 +};
 +
 +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 +      .num_chipselect = 4,
 +};
 +
 +static struct omap_hwmod omap34xx_mcspi1 = {
 +      .name           = "mcspi1",
 +      .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
 +      .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
 +      .main_clk       = "mcspi1_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
 +              },
 +      },
 +      .slaves         = omap34xx_mcspi1_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
 +      .class          = &omap34xx_mcspi_class,
 +      .dev_attr       = &omap_mcspi1_dev_attr,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +};
 +
 +/* mcspi2 */
 +static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
 +      { .name = "irq", .irq = 66 },
 +};
 +
 +static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
 +      { .name = "tx0", .dma_req = 43 },
 +      { .name = "rx0", .dma_req = 44 },
 +      { .name = "tx1", .dma_req = 45 },
 +      { .name = "rx1", .dma_req = 46 },
 +};
 +
 +static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
 +      &omap34xx_l4_core__mcspi2,
 +};
 +
 +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 +      .num_chipselect = 2,
 +};
 +
 +static struct omap_hwmod omap34xx_mcspi2 = {
 +      .name           = "mcspi2",
 +      .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
 +      .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
 +      .main_clk       = "mcspi2_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
 +              },
 +      },
 +      .slaves         = omap34xx_mcspi2_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
 +      .class          = &omap34xx_mcspi_class,
 +      .dev_attr       = &omap_mcspi2_dev_attr,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +};
 +
 +/* mcspi3 */
 +static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
 +      { .name = "irq", .irq = 91 }, /* 91 */
 +};
 +
 +static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
 +      { .name = "tx0", .dma_req = 15 },
 +      { .name = "rx0", .dma_req = 16 },
 +      { .name = "tx1", .dma_req = 23 },
 +      { .name = "rx1", .dma_req = 24 },
 +};
 +
 +static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
 +      &omap34xx_l4_core__mcspi3,
 +};
 +
 +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
 +      .num_chipselect = 2,
 +};
 +
 +static struct omap_hwmod omap34xx_mcspi3 = {
 +      .name           = "mcspi3",
 +      .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
 +      .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
 +      .main_clk       = "mcspi3_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
 +              },
 +      },
 +      .slaves         = omap34xx_mcspi3_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
 +      .class          = &omap34xx_mcspi_class,
 +      .dev_attr       = &omap_mcspi3_dev_attr,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +};
 +
 +/* SPI4 */
 +static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
 +      { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
 +};
 +
 +static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
 +      { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
 +      { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
 +};
 +
 +static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
 +      &omap34xx_l4_core__mcspi4,
 +};
 +
 +static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
 +      .num_chipselect = 1,
 +};
 +
 +static struct omap_hwmod omap34xx_mcspi4 = {
 +      .name           = "mcspi4",
 +      .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
 +      .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
 +      .main_clk       = "mcspi4_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
 +              },
 +      },
 +      .slaves         = omap34xx_mcspi4_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
 +      .class          = &omap34xx_mcspi_class,
 +      .dev_attr       = &omap_mcspi4_dev_attr,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +};
 +
+ /*
+  * usbhsotg
+  */
+ static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
+       .rev_offs       = 0x0400,
+       .sysc_offs      = 0x0404,
+       .syss_offs      = 0x0408,
+       .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                         SYSC_HAS_AUTOIDLE),
+       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                         MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+       .sysc_fields    = &omap_hwmod_sysc_type1,
+ };
+ static struct omap_hwmod_class usbotg_class = {
+       .name = "usbotg",
+       .sysc = &omap3xxx_usbhsotg_sysc,
+ };
+ /* usb_otg_hs */
+ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
+       { .name = "mc", .irq = 92 },
+       { .name = "dma", .irq = 93 },
+ };
+ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
+       .name           = "usb_otg_hs",
+       .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
+       .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
+       .main_clk       = "hsotgusb_ick",
+       .prcm           = {
+               .omap2 = {
+                       .prcm_reg_id = 1,
+                       .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
+                       .module_offs = CORE_MOD,
+                       .idlest_reg_id = 1,
+                       .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
+                       .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
+               },
+       },
+       .masters        = omap3xxx_usbhsotg_masters,
+       .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
+       .slaves         = omap3xxx_usbhsotg_slaves,
+       .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
+       .class          = &usbotg_class,
+       /*
+        * Erratum ID: i479  idle_req / idle_ack mechanism potentially
+        * broken when autoidle is enabled
+        * workaround is to disable the autoidle bit at module level.
+        */
+       .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+                               | HWMOD_SWSUP_MSTANDBY,
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ };
++
+ /* usb_otg_hs */
+ static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
+       { .name = "mc", .irq = 71 },
+ };
+ static struct omap_hwmod_class am35xx_usbotg_class = {
+       .name = "am35xx_usbotg",
+       .sysc = NULL,
+ };
+ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
+       .name           = "am35x_otg_hs",
+       .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
+       .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
+       .main_clk       = NULL,
+       .prcm = {
+               .omap2 = {
+               },
+       },
+       .masters        = am35xx_usbhsotg_masters,
+       .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
+       .slaves         = am35xx_usbhsotg_slaves,
+       .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
+       .class          = &am35xx_usbotg_class,
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
+ };
  static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_l3_main_hwmod,
        &omap3xxx_l4_core_hwmod,
        /* dma_system class*/
        &omap3xxx_dma_system_hwmod,
  
 +      /* mcspi class */
 +      &omap34xx_mcspi1,
 +      &omap34xx_mcspi2,
 +      &omap34xx_mcspi3,
 +      &omap34xx_mcspi4,
++
+       /* usbotg class */
+       &omap3xxx_usbhsotg_hwmod,
+       /* usbotg for am35x */
+       &am35xx_usbhsotg_hwmod,
        NULL,
  };