Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
index 1d5ad4c052d1a39bb41fd03a1b67b21a437a2db2..a1eb57c78f338ed933562918ca6b841acf964b0b 100644 (file)
--- a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
+++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
@@ -1491,6 +1491,9 @@ static int readVVVV(struct InternalInstruction* insn) {
   else
     return -1;
 
+  if (insn->mode != MODE_64BIT)
+    insn->vvvv &= 0x7;
+
   return 0;
 }
 

diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index cfaeb06d7244483a98970f6dec14cdbbde3fb32d..a9e6f41a7347aa0caa178224f825f29eb8ef890e 100644 (file)
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -365,3 +365,6 @@
 
 # CHECK: testq $0, %rax
 0x48 0xa9 0x00 0x00 0x00 0x00
+
+# CHECK: vaddps        %xmm3, %xmm15, %xmm0
+0xc4 0xe1 0x00 0x58 0xc3

diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt
index 24740f6c3138656ddb7188093fb7d2470f288075..35015c67d0c017968d68be669ad55693b4d7b6ec 100644 (file)
--- a/test/MC/Disassembler/X86/x86-32.txt
+++ b/test/MC/Disassembler/X86/x86-32.txt
@@ -384,3 +384,6 @@
 
 # CHECK: movl %eax, 0
 0xa3 0x00 0x00 0x00 0x00
+
+# CHECK: vaddps        %xmm3, %xmm7, %xmm0
+0xc4 0xe1 0x00 0x58 0xc3