[mips] Avoid redundant sign extension of the result of binary bitwise instructions.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7581

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229675 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 9e1b9d09d065f16b4147cdc1bee2a569d36a55f3..845191a61f153a8d2bec3cc0fd9dfd573e4c3e8f 100644 (file)
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -486,6 +486,14 @@ def : MipsPat<(trunc (assertzext GPR64:$src)),
 def : MipsPat<(i32 (trunc GPR64:$src)),
               (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
 
+// Bypass trunc nodes for bitwise ops.
+def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;

diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll
index 09d0ef9238af4400cd871bf1ae22636ff1cb7384..eec98831bd637ebdb97607b3a075a9094d4e0496 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/test/CodeGen/Mips/llvm-ir/and.ll
@@ -51,10 +51,7 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: and_i32:
 
-  ; GP32:         and     $2, $4, $5
-
-  ; GP64:         and     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          and     $2, $4, $5
 
   %r = and i32 %a, %b
   ret i32 %r

diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll
index 21d1d4fca2a360bc59e8ffc7582f189c5074e6d8..910f769ab5ad04a5afcea9abea9cdbe610ec0667 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/test/CodeGen/Mips/llvm-ir/or.ll
@@ -51,11 +51,7 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; GP32:         or     $2, $4, $5
-
-  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
-  ; FIXME: The sll instruction below is redundant.
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          or     $2, $4, $5
 
   %r = or i32 %a, %b
   ret i32 %r

diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll
index 94dead1eff41b01b34eb9fa3bc3c498cca055c5b..83107e32432039fc2a652045a3779e6eb18917d3 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -51,10 +51,7 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: xor_i32:
 
-  ; GP32:         xor     $2, $4, $5
-
-  ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          xor     $2, $4, $5
 
   %r = xor i32 %a, %b
   ret i32 %r