update D-phy driver,support one lane now.
>;
};
- isp:isp@0xFF910000{
+ isp:isp@ff910000{
compatible = "rockchip,isp";
- reg = <0xFF910000 0x10000>;
+ reg = <0xff910000 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&dummy>, <&clk_cif_out>;
clock_names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_vipout";
pinctrl-2 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1>;
pinctrl-3 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1 &isp_dvpd10d11>;
- status = "disabled";
+ status = "okay";
};
tsadc: tsadc@ff280000{
config CAMSYS_DRV
tristate "camsys driver "
- default n
+ default y
menu "RockChip camera system driver"
depends on CAMSYS_DRV
config CAMSYS_MRV
tristate "camsys driver for marvin isp "
- default n
+ default y
---help---
config CAMSYS_CIF
camsys_gpio_info_t *gpio_info;
camsys_gpio_t *gpio;
-
if ((devio->dev_id & CAMSYS_DEVID_EXTERNAL) == 0) {
err = -EINVAL;
camsys_err("dev_id: 0x%x is not support for camsys!",devio->dev_id);
goto end;
}
+#if 0
if (devio->phy.type == CamSys_Phy_Mipi) {
if (camsys_find_devmem(CAMSYS_REGISTER_MIPIPHY_RES_NAME, camsys_dev) == NULL) {
camsys_err("dev_id: 0x%x is connect to MIPI CSI, but %s isn't support",devio->dev_id,
goto end;
}
}
-
+#endif
extdev = camsys_find_extdev(devio->dev_id, camsys_dev);
if (extdev != NULL) {
gpio_info = &devio->pwrdn;
gpio = &extdev->pwrdn;
- for (i=0; i<4; i++) {
+ for (i=0; i<5; i++) {
if (strcmp(gpio_info->name,"NC")) {
gpio->io = camsys_gpio_get(gpio_info->name);
if (gpio->io < 0) {
camsys_dev->reset_cb(camsys_dev);
break;
}
+ #if 0
+ //for mipi
+ case CamSys_Gpio_Tag:
+ {
+ if((camsys_dev->mipiphy.ops )){
+ camsys_dev->mipiphy.ops(NULL,NULL,devctl->on);
+ }
+ }
+ #endif
default:
break;
err = -EINVAL;
goto end;
}
-
+#if 0
+ //zyc for test mipi
+ if((camsys_dev->mipiphy.ops ) && (irqcnnt->mis == MRV_ISP_MIS)){
+ camsys_dev->mipiphy.ops(NULL,NULL,0);
+ }
+#endif
+
spin_lock_irqsave(&camsys_dev->irq.lock,flags);
if (!list_empty(&camsys_dev->irq.irq_pool)) {
list_for_each_entry(irqpool, &camsys_dev->irq.irq_pool, list) {
list_add_tail(&irqstas->list,&irqpool->deactive);
spin_unlock_irqrestore(&irqpool->lock,flags);
} else {
- camsys_warn("Thread(pid: %d) wait irq timeout!!",current->pid);
+ // camsys_warn("Thread(pid: %d) wait irq timeout!!",current->pid);
err = -EAGAIN;
}
} else {
if (all == false) {
spin_lock_irqsave(&camsys_dev->irq.lock,flags);
- printk("%s++++++++++++++++\n",__func__);
if (!list_empty(&camsys_dev->irq.irq_pool)) {
list_for_each_entry(irqpool, &camsys_dev->irq.irq_pool, list) {
if (irqpool->pid == irqcnnt->pid) {
}
}
}
- printk("%s -------------\n",__func__);
spin_unlock_irqrestore(&camsys_dev->irq.lock,flags);
if (find_pool == false) {
if (copy_from_user((void*)&irqcnnt,(void __user *)arg, sizeof(camsys_irqcnnt_t)))
return -EFAULT;
- printk("disconnect ++++++++++++++++\n");
err = camsys_irq_disconnect(&irqcnnt,camsys_dev,false);
- printk("disconnect ----------------\n");
break;
}
.mmap = camsys_mmap,
};
-static int camsys_platform_probe_new(struct platform_device *pdev){
+static int camsys_platform_probe(struct platform_device *pdev){
int err = 0;
camsys_dev_t *camsys_dev;
struct resource register_res ;
unsigned long i2cmem;
camsys_meminfo_t *meminfo;
unsigned int irq_id;
-
err = of_address_to_resource(dev->of_node, 0, ®ister_res);
if (err < 0){
camsys_err("Get register resource from %s platform device failed!",pdev->name);
camsys_err("Mipi phy probe failed!");
}
}
-
+
+#if 0
if (strcmp(dev_name(&pdev->dev),CAMSYS_PLATFORM_MARVIN_NAME) == 0) {
#if (defined(CONFIG_CAMSYS_MRV))
camsys_mrv_probe_cb(pdev, camsys_dev);
camsys_err("CIF controller camsys driver haven't been complie!!!");
#endif
}
-
- camsys_trace(1, "%s memory:",dev_name(&pdev->dev));
- list_for_each_entry(meminfo, &camsys_dev->devmems.memslist, list) {
- if (strcmp(meminfo->name,CAMSYS_I2C_MEM_NAME) == 0) {
- camsys_dev->devmems.i2cmem = meminfo;
- camsys_trace(1," I2c memory (phy: 0x%x vir: 0x%x size: 0x%x)",
- meminfo->phy_base,meminfo->vir_base,meminfo->size);
- }
- if (strcmp(meminfo->name,CAMSYS_REGISTER_MEM_NAME) == 0) {
- camsys_dev->devmems.registermem = meminfo;
- camsys_trace(1," Register memory (phy: 0x%x vir: 0x%x size: 0x%x)",
- meminfo->phy_base,meminfo->vir_base,meminfo->size);
- }
- }
-
- camsys_dev->phy_cb = camsys_phy_ops;
- platform_set_drvdata(pdev,(void*)camsys_dev);
- //Camsys_devs list add
- spin_lock(&camsys_devs.lock);
- list_add_tail(&camsys_dev->list, &camsys_devs.devs);
- spin_unlock(&camsys_devs.lock);
-
-
- camsys_trace(1, "Probe %s device success ", dev_name(&pdev->dev));
- return 0;
-request_mem_fail:
- if (camsys_dev != NULL) {
-
- while(!list_empty(&camsys_dev->devmems.memslist)) {
- meminfo = list_first_entry(&camsys_dev->devmems.memslist, camsys_meminfo_t, list);
- if (meminfo) {
- list_del_init(&meminfo->list);
- if (strcmp(meminfo->name,CAMSYS_REGISTER_MEM_NAME)==0) {
- iounmap((void __iomem *)meminfo->vir_base);
- release_mem_region(meminfo->phy_base,meminfo->size);
- } else if (strcmp(meminfo->name,CAMSYS_I2C_MEM_NAME)==0) {
- kfree((void*)meminfo->vir_base);
- }
- kfree(meminfo);
- meminfo = NULL;
- }
- }
-
- kfree(camsys_dev);
- camsys_dev = NULL;
- }
-fail_end:
- return -1;
-
-
-}
-#if 0
-static int camsys_platform_probe(struct platform_device *pdev)
-{
- int err = 0;
- unsigned int irq_id;
- camsys_dev_t *camsys_dev;
- unsigned long i2cmem;
- camsys_meminfo_t *meminfo;
- struct resource *register_res, *mipiphy_register_res;
-
- camsys_trace(1, "Probe %s device now", dev_name(&pdev->dev));
- register_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, CAMSYS_REGISTER_RES_NAME);
- if (register_res == NULL) {
- camsys_err("Get register resource from %s platform device failed!",pdev->name);
- err = -ENODEV;
- goto fail_end;
- }
-
- mipiphy_register_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, CAMSYS_REGISTER_MIPIPHY_RES_NAME);
-
- irq_id = platform_get_irq_byname(pdev, CAMSYS_IRQ_RES_NAME);
- if (irq_id < 0) {
- camsys_err("Get irq resource from %s platform device failed!",pdev->name);
- err = -ENODEV;
- goto fail_end;
- }
-
- camsys_dev = (camsys_dev_t*)kzalloc(sizeof(camsys_dev_t), GFP_KERNEL);
- if (camsys_dev == NULL) {
- camsys_err("Allocate camsys_dev for %s platform device failed",pdev->name);
- err = -ENOMEM;
- goto fail_end;
- }
-
- //spin_lock_init(&camsys_dev->lock);
- mutex_init(&camsys_dev->extdevs.mut);
- INIT_LIST_HEAD(&camsys_dev->extdevs.list);
- INIT_LIST_HEAD(&camsys_dev->extdevs.active);
- INIT_LIST_HEAD(&camsys_dev->list);
-
-
- //IRQ init
- camsys_dev->irq.irq_id = irq_id;
- spin_lock_init(&camsys_dev->irq.lock);
- INIT_LIST_HEAD(&camsys_dev->irq.irq_pool);
- //init_waitqueue_head(&camsys_dev->irq.irq_done);
-
- INIT_LIST_HEAD(&camsys_dev->devmems.memslist);
- if (!request_mem_region(register_res->start, register_res->end - register_res->start + 1,
- dev_name(&pdev->dev))) {
- err = -ENOMEM;
- goto request_mem_fail;
- }
-
- //Register mem init
- meminfo = kzalloc(sizeof(camsys_meminfo_t),GFP_KERNEL);
- if (meminfo == NULL) {
- err = -ENOMEM;
- goto request_mem_fail;
- }
-
- meminfo->vir_base = (unsigned int)ioremap(register_res->start, register_res->end - register_res->start + 1);
- if (meminfo->vir_base == 0) {
- camsys_err("%s ioremap %s failed",dev_name(&pdev->dev), CAMSYS_REGISTER_MEM_NAME);
- err = -ENXIO;
- goto request_mem_fail;
- }
-
- strlcpy(meminfo->name, CAMSYS_REGISTER_MEM_NAME,sizeof(meminfo->name));
- meminfo->phy_base = register_res->start;
- meminfo->size = register_res->end - register_res->start + 1;
- list_add_tail(&meminfo->list, &camsys_dev->devmems.memslist);
-
- //I2c mem init
- i2cmem = __get_free_page(GFP_KERNEL);
- if (i2cmem == 0) {
- camsys_err("Allocate i2cmem failed!");
- err = -ENOMEM;
- goto request_mem_fail;
- }
- SetPageReserved(virt_to_page(i2cmem));
-
- meminfo = kzalloc(sizeof(camsys_meminfo_t),GFP_KERNEL);
- if (meminfo == NULL) {
- err = -ENOMEM;
- goto request_mem_fail;
- }
- strlcpy(meminfo->name,CAMSYS_I2C_MEM_NAME,sizeof(meminfo->name));
- meminfo->vir_base = i2cmem;
- meminfo->phy_base = virt_to_phys((void*)i2cmem);
- meminfo->size = PAGE_SIZE;
- list_add_tail(&meminfo->list, &camsys_dev->devmems.memslist);
-
- {
- unsigned int *tmpp;
-
- tmpp = (unsigned int*)meminfo->vir_base;
- *tmpp = 0xfa561243;
- }
-
- //Special init
-
- if (mipiphy_register_res) {
- if (camsys_mipiphy_probe_cb(pdev, camsys_dev) <0) {
- camsys_err("Mipi phy probe failed!");
- }
- }
-
- if (strcmp(dev_name(&pdev->dev),CAMSYS_PLATFORM_MARVIN_NAME) == 0) {
+#else
#if (defined(CONFIG_CAMSYS_MRV))
camsys_mrv_probe_cb(pdev, camsys_dev);
- #else
- camsys_err("Marvin controller camsys driver haven't been complie!!!");
- #endif
- } else {
- #if (defined(CONFIG_CAMSYS_CIF))
+ #elif (defined(CONFIG_CAMSYS_CIF))
camsys_cif_probe_cb(pdev,camsys_dev);
#else
- camsys_err("CIF controller camsys driver haven't been complie!!!");
+ camsys_err("camsys driver haven't been complie!!!");
#endif
- }
-
+#endif
camsys_trace(1, "%s memory:",dev_name(&pdev->dev));
list_for_each_entry(meminfo, &camsys_dev->devmems.memslist, list) {
if (strcmp(meminfo->name,CAMSYS_I2C_MEM_NAME) == 0) {
}
}
+
camsys_dev->phy_cb = camsys_phy_ops;
camsys_dev->pdev = pdev;
+
platform_set_drvdata(pdev,(void*)camsys_dev);
-
//Camsys_devs list add
spin_lock(&camsys_devs.lock);
list_add_tail(&camsys_dev->list, &camsys_devs.devs);
}
fail_end:
return -1;
+
+
}
-#endif
static int camsys_platform_remove(struct platform_device *pdev)
{
camsys_dev_t *camsys_dev = platform_get_drvdata(pdev);
static const struct of_device_id cif_of_match[] = {
- { .compatible = "rodkchip,isp" },
+ { .compatible = "rockchip,isp" },
};
MODULE_DEVICE_TABLE(of, cif_of_match);
{
.driver = {
.name = CAMSYS_PLATFORM_DRV_NAME,
- .of_match_table = cif_of_match,
+ .of_match_table = of_match_ptr(cif_of_match),
},
- .probe = camsys_platform_probe_new,
+ .probe = camsys_platform_probe,
.remove = (camsys_platform_remove),
};
-
+MODULE_ALIAS(CAMSYS_PLATFORM_DRV_NAME);
static int __init camsys_platform_init(void)
{
printk("CamSys driver version: v%d.%d.%d, CamSys head file version: v%d.%d.%d\n",
spin_lock_init(&camsys_devs.lock);
INIT_LIST_HEAD(&camsys_devs.devs);
platform_driver_register(&camsys_platform_driver);
-
+ // platform_driver_probe(&camsys_platform_driver, camsys_platform_probe_new);
return 0;
}
camsys_gpio_t rst;
camsys_gpio_t afpwr;
camsys_gpio_t afpwrdn;
+ camsys_gpio_t pwren;
camsys_flash_t fl;
static const char miscdev_name[] = CAMSYS_MARVIN_DEVNAME;
-
static int camsys_mrv_iomux_cb(camsys_extdev_t *extdev,void *ptr)
{
unsigned int cif_vol_sel;
}
}
+ //set 1.8v vol domain for rk32
+ __raw_writel(((1<<1)|(1<<(1+16))),RK_GRF_VIRT+0x0380);
+ __raw_writel(0xffffffff, RK_GRF_VIRT+0x01d4);
+
//set cif vol domain
if (extdev->phy.type == CamSys_Phy_Cif) {
__raw_writel(((1<<1)|(1<<(1+16))),RK30_GRF_BASE+0x018c);
}
#else
- __raw_writel(((1<<1)|(1<<(1+16))),RK_GRF_VIRT+0x018c);
+
+ //set 1.8v vol domain
+ __raw_writel(((1<<1)|(1<<(1+16))),RK_GRF_VIRT+0x0380);
#endif
//set driver strength
- __raw_writel(0xffffffff, RK_GRF_VIRT+0x01dc);
+ // __raw_writel(0xffffffff, RK_GRF_VIRT+0x01dc);
}
return 0;
camsys_dev_t *camsys_dev = (camsys_dev_t*)ptr;
camsys_mrv_clk_t *clk = (camsys_mrv_clk_t*)camsys_dev->clk;
- spin_lock(&clk->lock);
- if (on && !clk->in_on) {
- clk_enable(clk->pd_isp);
- clk_enable(clk->aclk_isp);
- clk_enable(clk->hclk_isp);
- clk_enable(clk->isp);
- clk_enable(clk->isp_jpe);
- clk_enable(clk->pclkin_isp);
+ // spin_lock(&clk->lock);
+ if (on && !clk->in_on) {
+ clk_set_rate(clk->isp,180000000);
+ clk_set_rate(clk->isp_jpe, 180000000);
+ // clk_set_rate(clk->aclk_isp,24000000);
+ // clk_set_rate(clk->hclk_isp,24000000);
+
+
+ clk_prepare_enable(clk->aclk_isp);
+ clk_prepare_enable(clk->hclk_isp);
+ clk_prepare_enable(clk->isp);
+ clk_prepare_enable( clk->isp_jpe);
+
+
+ // clk_enable(clk->pd_isp);
+ // clk_enable(clk->aclk_isp);
+ // clk_enable(clk->hclk_isp);
+ // clk_enable(clk->isp);
+ // clk_enable(clk->isp_jpe);
+ // clk_enable(clk->pclkin_isp);
clk->in_on = true;
camsys_mrv_reset_cb(ptr);
} else if (!on && clk->in_on) {
- clk_disable(clk->pd_isp);
- clk_disable(clk->aclk_isp);
- clk_disable(clk->hclk_isp);
- clk_disable(clk->isp);
- clk_disable(clk->isp_jpe);
- clk_disable(clk->pclkin_isp);
+
+
+ clk_disable_unprepare(clk->aclk_isp);
+ clk_disable_unprepare(clk->hclk_isp);
+ clk_disable_unprepare(clk->isp);
+ clk_disable_unprepare( clk->isp_jpe);
+
+ // clk_disable(clk->pd_isp);
+ // clk_disable(clk->aclk_isp);
+ // clk_disable(clk->hclk_isp);
+ // clk_disable(clk->isp);
+ // clk_disable(clk->isp_jpe);
+ // clk_disable(clk->pclkin_isp);
+
clk->in_on = false;
camsys_trace(1, "%s clock in turn off",dev_name(camsys_dev->miscdev.this_device));
}
- spin_unlock(&clk->lock);
+ // spin_unlock(&clk->lock);
return 0;
}
struct clk *cif_clk_out_div;
spin_lock(&clk->lock);
- if (on && (clk->out_on != on)) {
- clk_enable(clk->cif_clk_out);
+ if (on && (clk->out_on != on)) {
+ clk_prepare_enable(clk->cif_clk_out);
+
+// clk_enable(clk->cif_clk_out);
clk_set_rate(clk->cif_clk_out,on);
clk->out_on = on;
} else {
camsys_warn("%s clock out may be not off!", dev_name(camsys_dev->miscdev.this_device));
}
- clk_disable(clk->cif_clk_out);
+
+ clk_disable_unprepare( clk->cif_clk_out);
+// clk_disable(clk->cif_clk_out);
+
clk->out_on = 0;
camsys_trace(1, "%s clock out turn off",dev_name(camsys_dev->miscdev.this_device));
__raw_writel(isp_mis, (void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_ISP_ICR));
__raw_writel(mipi_mis, (void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MIPI_ICR));
__raw_writel(mi_mis, (void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_ICR));
-
+
spin_lock(&camsys_dev->irq.lock);
if (!list_empty(&camsys_dev->irq.irq_pool)) {
list_for_each_entry(irqpool, &camsys_dev->irq.irq_pool, list) {
// mrv_clk->pd_isp = devm_clk_get(&pdev->dev, "pd_isp");
mrv_clk->pd_isp = NULL;
- mrv_clk->aclk_isp = devm_clk_get(&pdev->dev, "aclk_isp");
- mrv_clk->hclk_isp = devm_clk_get(&pdev->dev, "hclk_isp");
+ mrv_clk->aclk_isp = devm_clk_get(&pdev->dev, "g_aclk_isp");
+ mrv_clk->hclk_isp = devm_clk_get(&pdev->dev, "g_hclk_isp");
mrv_clk->isp = devm_clk_get(&pdev->dev, "clk_isp");
mrv_clk->isp_jpe = devm_clk_get(&pdev->dev, "clk_isp_jpe");
mrv_clk->pclkin_isp = devm_clk_get(&pdev->dev, "pclkin_isp");
- mrv_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_vipout");
+ mrv_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_cif_out");
+
if (/*IS_ERR_OR_NULL(mrv_clk->pd_isp) ||*/ IS_ERR_OR_NULL(mrv_clk->aclk_isp) || IS_ERR_OR_NULL(mrv_clk->hclk_isp) ||
- IS_ERR_OR_NULL(mrv_clk->isp) || IS_ERR_OR_NULL(mrv_clk->isp_jpe) || IS_ERR_OR_NULL(mrv_clk->pclkin_isp) ||
+ IS_ERR_OR_NULL(mrv_clk->isp) || IS_ERR_OR_NULL(mrv_clk->isp_jpe) /*|| IS_ERR_OR_NULL(mrv_clk->pclkin_isp)*/ ||
IS_ERR_OR_NULL(mrv_clk->cif_clk_out)) {
camsys_err("Get %s clock resouce failed!\n",miscdev_name);
err = -EINVAL;
goto clk_failed;
}
+
- clk_set_rate(mrv_clk->isp,320000000);
- clk_set_rate(mrv_clk->isp_jpe,320000000);
+// clk_set_rate(mrv_clk->isp,1800000000);
+// clk_set_rate(mrv_clk->isp_jpe,180000000);
spin_lock_init(&mrv_clk->lock);
#define DPHY_RX0_TESTEN (1<<2)
#define DPHY_RX0_TESTDIN_OFFSET (3)
+#define DPHY_TX1RX1_ENABLECLK_MASK (0x1<<28)
+#define DPHY_RX1_SRC_SEL_MASK (0x1<<29)
+#define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1<<30)
+#define DPHY_TX1RX1_BASEDIR_OFFSET (0x1<<31)
+
+#define DPHY_TX1RX1_ENABLECLK (0x1<<12)
+#define DPHY_TX1RX1_DISABLECLK (0x0<<12)
+#define DPHY_RX1_SRC_SEL_ISP (0x1<<13)
+#define DPHY_TX1RX1_SLAVEZ (0x0<<14)
+#define DPHY_TX1RX1_BASEDIR_REC (0x1<<15)
+
+
//GRF_SOC_CON6
//bit 0 grf_con_disable_isp
//bit 1 grf_con_isp_dphy_sel 1'b0 mipi phy rx0
#define GRF_SOC_CON6_OFFSET (0x025c)
-#define MIPI_PHY_RX0_MASK (0x1<<16)
-#define MIPI_PHY_RX0 (0x1<<0)
+#define MIPI_PHY_DISABLE_ISP_MASK (0x1<<16)
+#define MIPI_PHY_DISABLE_ISP (0x0<<0)
+
+#define DSI_CSI_TESTBUS_SEL_MASK (0x1<<30)
+#define DSI_CSI_TESTBUS_SEL_OFFSET_BIT (14)
+
+
+#define MIPI_PHY_DPHYSEL_OFFSET_MASK (0x1<<17)
+#define MIPI_PHY_DPHYSEL_OFFSET_BIT (0x1)
+
+//GRF_SOC_CON10
+//bit12:15 grf_dphy_rx0_enable
+//bit 0:3 turn disable
+#define GRF_SOC_CON10_OFFSET (0x026c)
+#define DPHY_RX0_TURN_DISABLE_MASK (0xf<<16)
+#define DPHY_RX0_TURN_DISABLE_OFFSET_BITS (0x0)
+#define DPHY_RX0_ENABLE_MASK (0xf<<28)
+#define DPHY_RX0_ENABLE_OFFSET_BITS (12)
+
+//GRF_SOC_CON9
+//bit12:15 grf_dphy_rx0_enable
+//bit 0:3 turn disable
+#define GRF_SOC_CON9_OFFSET (0x0268)
+#define DPHY_TX1RX1_TURN_DISABLE_MASK (0xf<<16)
+#define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS (0x0)
+#define DPHY_TX1RX1_ENABLE_MASK (0xf<<28)
+#define DPHY_TX1RX1_ENABLE_OFFSET_BITS (12)
+
+//GRF_SOC_CON15
+//bit 0:3 turn request
+#define GRF_SOC_CON15_OFFSET (0x03a4)
+#define DPHY_RX0_TURN_REQUEST_MASK (0xf<<16)
+#define DPHY_RX0_TURN_REQUEST_OFFSET_BITS (0x0)
+
+#define DPHY_TX1RX1_TURN_REQUEST_MASK (0xf<<20)
+#define DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS (0x0)
+
#endif
-static void phy0_WriteReg(uint8_t addr, uint8_t data)
+
+static void phy_select(uint8_t index)
{
+ if((index == 0) || (index == 1)){
+ write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DPHYSEL_OFFSET_MASK | (index<<MIPI_PHY_DPHYSEL_OFFSET_BIT));
+ if(index == 1){
+ write_grf_reg(GRF_SOC_CON6_OFFSET, DSI_CSI_TESTBUS_SEL_MASK | (1<<DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
+
+ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX1_SRC_SEL_ISP | DPHY_RX1_SRC_SEL_MASK);
+ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_SLAVEZ | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
+ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_BASEDIR_REC | DPHY_TX1RX1_BASEDIR_OFFSET);
+ }
+
+ }else{
+ camsys_err("phy index is erro!");
+
+ }
+}
+
+static void phy0_WriteReg(uint8_t addr, uint8_t data)
+{
+ // uint8_t test_data = 0;
//TESTEN =1,TESTDIN=addr
write_grf_reg(GRF_SOC_CON14_OFFSET,(( addr << DPHY_RX0_TESTDIN_OFFSET) |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN| DPHY_RX0_TESTEN_MASK));
+// //TESTCLK=1
+ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
+
//TESTCLK=0
- write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
- //TESTEN =0,TESTDIN=data
- write_grf_reg(GRF_SOC_CON14_OFFSET, (( data << DPHY_RX0_TESTDIN_OFFSET)|DPHY_RX0_TESTDIN_MASK |DPHY_RX0_TESTEN));
- //TESTCLK=1
- write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
+ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
+
+ if(data != -1){ //write data ?
+ //TESTEN =0,TESTDIN=data
+ write_grf_reg(GRF_SOC_CON14_OFFSET, (( data << DPHY_RX0_TESTDIN_OFFSET)|DPHY_RX0_TESTDIN_MASK |DPHY_RX0_TESTEN));
+ //TESTCLK=1
+ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
+ }
}
-static uint8_t phy0_ReadReg(uint8_t addr) //read 0xff968034 bit8~15
+static uint8_t phy0_ReadReg(uint8_t addr)
{
uint8_t data = 0;
+
//TESTEN =1,TESTDIN=addr
write_grf_reg(GRF_SOC_CON14_OFFSET,(( addr << DPHY_RX0_TESTDIN_OFFSET) |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN| DPHY_RX0_TESTEN_MASK));
+
//TESTCLK=0
write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
- data = ((read_grf_reg(GRF_SOC_CON14_OFFSET) >> DPHY_RX0_TESTDIN_OFFSET) & (0xff));
-
- camsys_err("%s phy addr = 0x%x,value = 0x%x\n",__func__,addr,data);
return data ;
}
-
-static void PHY0_Init(int numLane,int clkfreq)
+static void phy_config_num_lane(uint8_t index,int numLane)
{
-
-// select phy rx0
- write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_RX0_MASK | MIPI_PHY_RX0);
+ uint8_t lane_mask =0;
+ int i = 0;
+ for(i=0;i<numLane;i++){
+ lane_mask |= 1<<i;
+ }
+ camsys_trace(1,"lane num = 0x%d\n",lane_mask);
+ if(index == 0){
+ // set lane num
+ write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_ENABLE_MASK | (lane_mask << DPHY_RX0_ENABLE_OFFSET_BITS));
+ // set lan turndisab as 1
+ write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_TURN_DISABLE_MASK | (0xf << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
+
+ write_grf_reg(GRF_SOC_CON10_OFFSET, (0xc<<4)|(0xf<<20));
+
+ // set lan turnrequest as 0
+ write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_RX0_TURN_REQUEST_MASK | (0x0 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
+ }else if(index == 1){
+ // set lane num
+ write_grf_reg(GRF_SOC_CON9_OFFSET, DPHY_TX1RX1_ENABLE_MASK | (lane_mask << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
+ // set lan turndisab as 1
+ write_grf_reg(GRF_SOC_CON9_OFFSET, DPHY_TX1RX1_TURN_DISABLE_MASK | (0xf << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
+ // set lan turnrequest as 0
+ write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_TX1RX1_TURN_REQUEST_MASK | (0x0 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
+ }
+}
+
+static void phy0_start(int freq,int numLane)
+{
//TESTCLK=1
write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
//TESTCLR=1
- write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK | DPHY_RX0_TESTCLR_MASK |DPHY_RX0_TESTCLR);
+ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK |DPHY_RX0_TESTCLR);
//TESTCLR=0 zyc
- write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
+// write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK);
+ udelay(1000);
//**********************************************************************//
+#if 1
//set clock lane
phy0_WriteReg(0x34,0x14);
360M 0x2A
*******************/
phy0_WriteReg(0x44,0x10);
+ if(numLane > 1)
+ phy0_WriteReg(0x54,0x10);
+#endif
//**********************************************************************//
//Normal operation
- phy0_ReadReg(0x00);
+ phy0_WriteReg(0x0,-1);
//TESTCLK=1
write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
//TESTEN =0
- write_grf_reg(GRF_SOC_CON14_OFFSET, (DPHY_RX0_TESTEN));
+ write_grf_reg(GRF_SOC_CON14_OFFSET, (DPHY_RX0_TESTEN_MASK));
+
+}
- }
static int camsys_mipiphy_ops (void *phy, void *phyinfo, unsigned int on)
{
- PHY0_Init(1,0);
+#if 0
+ camsys_phyinfo_t* phyinfo_s = (camsys_phyinfo_t*)phyinfo;
+ struct camsys_mipiphy_s* phy_s = (struct camsys_mipiphy_s*)phy;
+ if(phy_s->phy_index == 0){
+ phy_select(phy_s->phy_index);
+ phy_config_num_lane(phy_s->data_en_bit);
+ phy0_start(0,phy_s->data_en_bit);
+
+ }else if(phy_s->phy_index == 1){
+
+ }else{
+
+ camsys_err("phy index is erro!");
+ }
+#else
+#if 0
+ if(on == 1){
+ //disable isp
+ write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DISABLE_ISP_MASK | 1);
+ phy_select(0);
+ // phy_config_num_lane(0,2);
+ phy0_start(0,2);
+
+ phy_config_num_lane(0,2);
+ udelay(200);
+ //enable isp
+ write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DISABLE_ISP_MASK | 0);
+ }else
+#endif
+ {
+ //disable isp
+ write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DISABLE_ISP_MASK | 1);
+ phy_select(0);
+ // phy_config_num_lane(0,2);
+ phy0_start(0,1);
+
+ phy_config_num_lane(0,1);
+ udelay(200);
+ //enable isp
+ write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DISABLE_ISP_MASK | 0);
+ }
+
+#endif
return 0;
}
camsys_dev->mipiphy.ops = camsys_mipiphy_ops;
camsys_dev->mipiphy.remove = camsys_mipiphy_remove_cb;
+
return 0;
}
* 1) add support cif phy for marvin;
*v0.0.4:
* 1) add clock information in struct camsys_devio_name_s;
+*v0.0.5:
+ 1) add pwren control
*/
-#define CAMSYS_HEAD_VERSION KERNEL_VERSION(0,0,4)
+#define CAMSYS_HEAD_VERSION KERNEL_VERSION(0,0,5)
#define CAMSYS_MARVIN_DEVNAME "camsys_marvin"
#define CAMSYS_CIF0_DEVNAME "camsys_cif0"
CamSys_Rst,
CamSys_AfPwr,
CamSys_AfPwrDn,
-
+ CamSys_PwrEn,
+
CamSys_Gpio_Tag = 50,
CamSys_ClkIn
typedef struct camsys_mipiphy_s {
unsigned int data_en_bit; //data lane enable bit;
+ #if 0
+ unsigned int freq;
+ unsigned int phy_index; //phy0,phy1
+ #endif
} camsys_mipiphy_t;
typedef enum camsys_fmt_e {
camsys_regulator_info_t afvdd;
camsys_gpio_info_t pwrdn; // standby gpio name
- camsys_gpio_info_t rst; // hard reset gpio name
+ camsys_gpio_info_t rst; // hard reset gpio name
camsys_gpio_info_t afpwr; // auto focus vcm driver ic power gpio name
camsys_gpio_info_t afpwrdn; // auto focus vcm driver ic standby gpio
+ camsys_gpio_info_t pwren; // power enable gpio name
+
camsys_flash_info_t fl;
projects / firefly-linux-kernel-4.4.55.git / commitdiff