ARMPseudoInst instructions should default to being considered a single 4-byte

instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119713 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index e84b98d10036521ee2e1c2ef4a806e2c8373d4d2..3533ce68593f855039cbb44eb6e90ca9049b4c5c 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -249,6 +249,9 @@ class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
 class ARMPseudoInst<dag oops, dag iops, InstrItinClass itin,
                     list<dag> pattern>
   : PseudoInst<oops, iops, itin, pattern> {
+  // Default these to 4byte size, as they're almost always expanded to a
+  // single instruction. Any exceptions can override the SZ field value.
+  let SZ = Size4Bytes;
   list<Predicate> Predicates = [IsARM];
 }