Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly

hardfloat case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 252d920e6c22dd3bd05c84cfc9e811e98fb8f28e..155ef591f539e0d5fa050f691beb6e46b6097518 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1461,21 +1461,17 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
       } else {
         TargetRegisterClass *RC;
 
-        if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32)
+        if (RegVT == MVT::f32)
           RC = ARM::SPRRegisterClass;
-        else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)
+        else if (RegVT == MVT::f64)
           RC = ARM::DPRRegisterClass;
-        else if (FloatABIType == FloatABI::Hard && RegVT == MVT::v2f64)
+        else if (RegVT == MVT::v2f64)
           RC = ARM::QPRRegisterClass;
-        else if (AFI->isThumb1OnlyFunction())
-          RC = ARM::tGPRRegisterClass;
+        else if (RegVT == MVT::i32)
+          RC = (AFI->isThumb1OnlyFunction() ?
+                ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
         else
-          RC = ARM::GPRRegisterClass;
-
-        assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
-                (FloatABIType == FloatABI::Hard &&
-                 ((RegVT == MVT::f64) || (RegVT == MVT::v2f64)))) &&
-               "RegVT not supported by FORMAL_ARGUMENTS Lowering");
+          llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
 
         // Transform the arguments in physical registers into virtual ones.
         unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);