Make the x86 asm flavor part of the subtarget info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30146 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index 3fdd7b16672e917be4a60abff47a3d23742ffc88..2e32f34506b6253d0adfbf44e68cc28935df5259 100644 (file)
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -23,28 +23,11 @@
 #include "llvm/Type.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/Support/Mangler.h"
-#include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
-enum AsmWriterFlavorTy { att, intel };
-
 Statistic<> llvm::EmittedInsts("asm-printer",
                                "Number of machine instrs printed");
 
-cl::opt<AsmWriterFlavorTy>
-AsmWriterFlavor("x86-asm-syntax",
-                cl::desc("Choose style of code to emit from X86 backend:"),
-                cl::values(
-                           clEnumVal(att,   "  Emit AT&T-style assembly"),
-                           clEnumVal(intel, "  Emit Intel-style assembly"),
-                           clEnumValEnd),
-#ifdef _MSC_VER
-                cl::init(intel)
-#else
-                cl::init(att)
-#endif
-                );
-
 X86TargetAsmInfo::X86TargetAsmInfo(X86TargetMachine &TM) {
   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
   
@@ -97,7 +80,7 @@ X86TargetAsmInfo::X86TargetAsmInfo(X86TargetMachine &TM) {
   default: break;
   }
   
-  if (AsmWriterFlavor == intel) {
+  if (Subtarget->isFlavorIntel()) {
     GlobalPrefix = "_";
     CommentString = ";";
   
@@ -271,12 +254,12 @@ bool X86SharedAsmPrinter::doFinalization(Module &M) {
 ///
 FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,
                                              X86TargetMachine &tm) {
+  const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
   TargetAsmInfo *TAI = new X86TargetAsmInfo(tm);
 
-  switch (AsmWriterFlavor) {
-  default:
-    assert(0 && "Unknown asm flavor!");
-  case intel: return new X86IntelAsmPrinter(o, tm, TAI);
-  case att: return new X86ATTAsmPrinter(o, tm, TAI);
+  if (Subtarget->isFlavorIntel()) {
+    return new X86IntelAsmPrinter(o, tm, TAI);
+  } else {
+    return new X86ATTAsmPrinter(o, tm, TAI);
   }
 }

diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index 2c2acec299a5e571c3776dd1acc169e40bdb4ee4..5107f912f36582af0f90e19e1d1b24cbae81b455 100644 (file)
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -13,9 +13,24 @@
 
 #include "X86Subtarget.h"
 #include "llvm/Module.h"
+#include "llvm/Support/CommandLine.h"
 #include "X86GenSubtarget.inc"
 using namespace llvm;
 
+cl::opt<X86Subtarget::AsmWriterFlavorTy>
+AsmWriterFlavor("x86-asm-syntax",
+  cl::desc("Choose style of code to emit from X86 backend:"),
+  cl::values(
+    clEnumValN(X86Subtarget::att,   "att",   "  Emit AT&T-style assembly"),
+    clEnumValN(X86Subtarget::intel, "intel", "  Emit Intel-style assembly"),
+    clEnumValEnd),
+#ifdef _MSC_VER
+  cl::init(X86Subtarget::intel)
+#else
+  cl::init(X86Subtarget::att)
+#endif
+                );
+
 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
 /// specified arguments.  If we can't run cpuid on the host, return true.
 static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
@@ -151,6 +166,7 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS) {
   MinRepStrSizeThreshold = 128;
   X86SSELevel = NoMMXSSE;
   X863DNowLevel = NoThreeDNow;
+  AsmFlavor = AsmWriterFlavor;
   Is64Bit = false;
 
   // Determine default and user specified characteristics

diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
index 24247ba6ab3c591fc40b020e1809151beab2f0a5..84e5e296121423fd65c919590d40b0a193bba59b 100644 (file)
--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@@ -22,6 +22,11 @@ namespace llvm {
 class Module;
 
 class X86Subtarget : public TargetSubtarget {
+public:
+  enum AsmWriterFlavorTy {
+    att, intel
+  };
+
 protected:
   enum X86SSEEnum {
     NoMMXSSE, MMX, SSE1, SSE2, SSE3
@@ -31,12 +36,15 @@ protected:
     NoThreeDNow, ThreeDNow, ThreeDNowA
   };
 
+  /// AsmFlavor - Which x86 asm dialect to use.
+  AsmWriterFlavorTy AsmFlavor;
+
   /// X86SSELevel - MMX, SSE1, SSE2, SSE3, or none supported.
   X86SSEEnum X86SSELevel;
 
   /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
   X863DNowEnum X863DNowLevel;
-
+  
   /// Is64Bit - True if the processor supports Em64T.
   bool Is64Bit;
 
@@ -80,6 +88,9 @@ public:
   bool hasSSE3() const { return X86SSELevel >= SSE3; }
   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
+  
+  bool isFlavorAtt() const { return AsmFlavor == att; }
+  bool isFlavorIntel() const { return AsmFlavor == intel; }
 
   bool isTargetDarwin() const { return TargetType == isDarwin; }
   bool isTargetELF() const { return TargetType == isELF; }