TargetCacheInfo has been removed; its only uses were to propagate a constant

(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12043 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetCacheInfo.h b/include/llvm/Target/TargetCacheInfo.h
deleted file mode 100644 (file)
index 357adf0..0000000
--- a/include/llvm/Target/TargetCacheInfo.h
+++ /dev/null
@@ -1,66 +0,0 @@
-//===-- llvm/Target/TargetCacheInfo.h ---------------------------*- C++ -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-//  Describes properties of the target cache architecture.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETCACHEINFO_H
-#define LLVM_TARGET_TARGETCACHEINFO_H
-
-#include "Support/DataTypes.h"
-
-namespace llvm {
-
-class TargetMachine;
-
-struct TargetCacheInfo {
-  const TargetMachine ⌖
-  TargetCacheInfo(const TargetCacheInfo&); // DO NOT IMPLEMENT
-  void operator=(const TargetCacheInfo&);  // DO NOT IMPLEMENT
-protected:
-  unsigned int           numLevels;
-  std::vector<unsigned short> cacheLineSizes;
-  std::vector<unsigned int>   cacheSizes;
-  std::vector<unsigned short> cacheAssoc;
-  
-public:
-  TargetCacheInfo(const TargetMachine& tgt) : target(tgt) {
-    Initialize();
-  }
-  virtual ~TargetCacheInfo() {}
-  
-  // Default parameters are:
-  //    NumLevels    = 2
-  //    L1: LineSize 16, Cache Size 32KB, Direct-mapped (assoc = 1)
-  //    L2: LineSize 32, Cache Size 1 MB, 4-way associative
-  // NOTE: Cache levels are numbered from 1 as above, not from 0.
-  // 
-  virtual  void     Initialize          (); // subclass to override defaults
-  
-  unsigned int      getNumCacheLevels   () const {
-    return numLevels;
-  }
-  unsigned short    getCacheLineSize    (unsigned level)  const {
-    assert(level <= cacheLineSizes.size() && "Invalid cache level");
-    return cacheLineSizes[level-1];
-  }
-  unsigned int      getCacheSize        (unsigned level)  const {
-    assert(level <= cacheSizes.size() && "Invalid cache level");
-    return cacheSizes[level-1];
-  }
-  unsigned short    getCacheAssoc       (unsigned level)  const {
-    assert(level <= cacheAssoc.size() && "Invalid cache level");
-    return cacheAssoc[level];
-  }
-};
-
-} // End llvm namespace
-
-#endif

diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index a653d6a47f2ca5b6578ade102239ef409dea47f9..7d9586c2f86b652648c35df02a3560a4daeb8c37 100644 (file)
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -25,7 +25,6 @@ class TargetJITInfo;
 class TargetSchedInfo;
 class TargetRegInfo;
 class TargetFrameInfo;
-class TargetCacheInfo;
 class MachineCodeEmitter;
 class MRegisterInfo;
 class FunctionPassManager;
@@ -75,7 +74,6 @@ public:
   virtual const TargetSchedInfo&        getSchedInfo() const = 0;
   virtual const TargetRegInfo&          getRegInfo()   const = 0;
   virtual const TargetFrameInfo&        getFrameInfo() const = 0;
-  virtual const TargetCacheInfo&        getCacheInfo() const = 0;
   const TargetData &getTargetData() const { return DataLayout; }
 
   /// getRegisterInfo - If register information is available, return it.  If

diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp
index 983eed76ef38849b380a18783b7d87d1bc6fb28b..3f038945726d51a16f615155a953b9190cccad8c 100644 (file)
--- a/lib/CodeGen/MachineFunction.cpp
+++ b/lib/CodeGen/MachineFunction.cpp
@@ -22,7 +22,6 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/Target/TargetCacheInfo.h"
 #include "llvm/Function.h"
 #include "llvm/iOther.h"
 using namespace llvm;
@@ -273,7 +272,7 @@ ComputeMaxOptionalArgsSize(const TargetMachine& target, const Function *F,
 inline unsigned
 SizeToAlignment(unsigned size, const TargetMachine& target)
 {
-  unsigned short cacheLineSize = target.getCacheInfo().getCacheLineSize(1); 
+  const unsigned short cacheLineSize = 16;
   if (size > (unsigned) cacheLineSize / 2)
     return cacheLineSize;
   else

diff --git a/lib/Target/CBackend/CTargetMachine.h b/lib/Target/CBackend/CTargetMachine.h
index 53e01471ea39e9bd87733d8f42699167414907cf..dba714d2ff9b4f493d71d30fade1183f7d5cd03b 100644 (file)
--- a/lib/Target/CBackend/CTargetMachine.h
+++ b/lib/Target/CBackend/CTargetMachine.h
@@ -27,7 +27,6 @@ struct CTargetMachine : public TargetMachine {
   virtual const TargetFrameInfo &getFrameInfo() const { abort(); }
   virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
   virtual const TargetRegInfo   &getRegInfo()   const { abort(); }
-  virtual const TargetCacheInfo &getCacheInfo() const { abort(); }
 
   // This is the only thing that actually does anything here.
   virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);

diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h
index ae77fb293543f0a09cd0a8bd2c0445b483d2df0e..13f655ab1f1e7098e6a3370975e2766cafdcc800 100644 (file)
--- a/lib/Target/Sparc/SparcTargetMachine.h
+++ b/lib/Target/Sparc/SparcTargetMachine.h
@@ -42,7 +42,6 @@ public:
 
   virtual const TargetSchedInfo &getSchedInfo()  const { abort(); }
   virtual const TargetRegInfo   &getRegInfo()    const { abort(); }
-  virtual const TargetCacheInfo  &getCacheInfo() const { abort(); }
 
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle

diff --git a/lib/Target/SparcV8/SparcV8TargetMachine.h b/lib/Target/SparcV8/SparcV8TargetMachine.h
index ae77fb293543f0a09cd0a8bd2c0445b483d2df0e..13f655ab1f1e7098e6a3370975e2766cafdcc800 100644 (file)
--- a/lib/Target/SparcV8/SparcV8TargetMachine.h
+++ b/lib/Target/SparcV8/SparcV8TargetMachine.h
@@ -42,7 +42,6 @@ public:
 
   virtual const TargetSchedInfo &getSchedInfo()  const { abort(); }
   virtual const TargetRegInfo   &getRegInfo()    const { abort(); }
-  virtual const TargetCacheInfo  &getCacheInfo() const { abort(); }
 
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle

diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 146f11c899b0734d67accae66c58e577dff43d07..0fa4c49ceb4b89a3f2aada1b53fae58bc19f57a9 100644 (file)
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -119,7 +119,7 @@ namespace {
   /// 
   inline unsigned int
   SizeToAlignment(unsigned int size, const TargetMachine& target) {
-    unsigned short cacheLineSize = target.getCacheInfo().getCacheLineSize(1); 
+    const unsigned short cacheLineSize = 16;
     if (size > (unsigned) cacheLineSize / 2)
       return cacheLineSize;
     else

diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index d0e03ed52c4a3daeee8d2030cc0d92a4ebd71bec..20ebc424eeba8006b83814ec3be55da33d9d8aca 100644 (file)
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -19,7 +19,6 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetSchedInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/Target/TargetCacheInfo.h"
 #include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Type.h"
 #include "SparcV9RegClassInfo.h"
@@ -89,19 +88,6 @@ protected:
   virtual void initializeResources();
 };
 
-//---------------------------------------------------------------------------
-// class SparcV9CacheInfo 
-// 
-// Purpose:
-//   Interface to cache parameters for the UltraSPARC.
-//   Just use defaults for now.
-//---------------------------------------------------------------------------
-
-struct SparcV9CacheInfo: public TargetCacheInfo {
-  SparcV9CacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {} 
-};
-
-
 /// createStackSlotsPass - External interface to stack-slots pass that enters 2
 /// empty slots at the top of each function stack
 ///

diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index 9611c1041ec96b30abcec0cab4a24c83b681fc69..92c670c83472c20db6809a97bc23abf069deceae 100644 (file)
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -116,7 +116,6 @@ SparcV9TargetMachine::SparcV9TargetMachine(IntrinsicLowering *il)
     schedInfo(*this),
     regInfo(*this),
     frameInfo(*this),
-    cacheInfo(*this),
     jitInfo(*this) {
 }
 

diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.h b/lib/Target/SparcV9/SparcV9TargetMachine.h
index 75a780c22fcdd25d0563a16f1cb387a2600101f5..424dcd11e42a4665c92f21702cd9e10f8fe98c48 100644 (file)
--- a/lib/Target/SparcV9/SparcV9TargetMachine.h
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.h
@@ -30,7 +30,6 @@ class SparcV9TargetMachine : public TargetMachine {
   SparcV9SchedInfo schedInfo;
   SparcV9RegInfo   regInfo;
   SparcV9FrameInfo frameInfo;
-  SparcV9CacheInfo cacheInfo;
   SparcV9JITInfo   jitInfo;
 public:
   SparcV9TargetMachine(IntrinsicLowering *IL);
@@ -39,7 +38,6 @@ public:
   virtual const TargetSchedInfo  &getSchedInfo() const { return schedInfo; }
   virtual const TargetRegInfo    &getRegInfo()   const { return regInfo; }
   virtual const TargetFrameInfo  &getFrameInfo() const { return frameInfo; }
-  virtual const TargetCacheInfo  &getCacheInfo() const { return cacheInfo; }
   virtual       TargetJITInfo    *getJITInfo()         { return &jitInfo; }
 
   virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);

diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
index 51c1222ab68e69eb6a60af1339f6d130e088f190..30199be06ae08931d34b1702514ba064cdda7a57 100644 (file)
--- a/lib/Target/TargetMachine.cpp
+++ b/lib/Target/TargetMachine.cpp
@@ -8,12 +8,10 @@
 //===----------------------------------------------------------------------===//
 //
 // This file describes the general parts of a Target machine.
-// This file also implements TargetCacheInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetCacheInfo.h"
 #include "llvm/Type.h"
 #include "llvm/IntrinsicLowering.h"
 using namespace llvm;
@@ -33,15 +31,10 @@ TargetMachine::TargetMachine(const std::string &name, IntrinsicLowering *il,
   IL = il ? il : new DefaultIntrinsicLowering();
 }
 
-
-
 TargetMachine::~TargetMachine() {
   delete IL;
 }
 
-
-
-
 unsigned TargetMachine::findOptimalStorageSize(const Type *Ty) const {
   // All integer types smaller than ints promote to 4 byte integers.
   if (Ty->isIntegral() && Ty->getPrimitiveSize() < 4)
@@ -49,15 +42,3 @@ unsigned TargetMachine::findOptimalStorageSize(const Type *Ty) const {
 
   return DataLayout.getTypeSize(Ty);
 }
-
-
-//---------------------------------------------------------------------------
-// TargetCacheInfo Class
-//
-
-void TargetCacheInfo::Initialize() {
-  numLevels = 2;
-  cacheLineSizes.push_back(16);  cacheLineSizes.push_back(32); 
-  cacheSizes.push_back(1 << 15); cacheSizes.push_back(1 << 20);
-  cacheAssoc.push_back(1);       cacheAssoc.push_back(4);
-}

diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
index be8d8879a122409f496304111ede7414d61f4c9c..de85f95f73aebfc635e896c251399937bb57a736 100644 (file)
--- a/lib/Target/X86/X86TargetMachine.h
+++ b/lib/Target/X86/X86TargetMachine.h
@@ -32,18 +32,14 @@ public:
 
   virtual const X86InstrInfo     &getInstrInfo() const { return InstrInfo; }
   virtual const TargetFrameInfo  &getFrameInfo() const { return FrameInfo; }
-  virtual const MRegisterInfo *getRegisterInfo() const {
+  virtual       TargetJITInfo    *getJITInfo()         { return &JITInfo; }
+  virtual const MRegisterInfo    *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
 
-  virtual TargetJITInfo *getJITInfo() {
-    return &JITInfo;
-  }
-
-
-  virtual const TargetSchedInfo &getSchedInfo()  const { abort(); }
-  virtual const TargetRegInfo   &getRegInfo()    const { abort(); }
-  virtual const TargetCacheInfo  &getCacheInfo() const { abort(); }
+  // deprecated interfaces
+  virtual const TargetSchedInfo  &getSchedInfo() const { abort(); }
+  virtual const TargetRegInfo    &getRegInfo()   const { abort(); }
 
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle