"lghi\t{$dst, $src}",
[(set GR64:$dst, imm:$src)]>;
}
+
+//===----------------------------------------------------------------------===//
+// Arithmetic Instructions
+
+let isTwoAddress = 1 in {
+
+let Defs = [PSW] in {
+
+let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
+// FIXME: Provide proper encoding!
+def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+ "agr\t{$dst, $src2}",
+ [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
+ (implicit PSW)]>;
+}
+
+// FIXME: Provide proper encoding!
+def ADD64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "aghi\t{$dst, $src2}",
+ [(set GR64:$dst, (add GR64:$src1, imm:$src2)),
+ (implicit PSW)]>;
+
+} // Defs = [PSW]
+} // isTwoAddress = 1
def F14 : FPR<14, "f14">, DwarfRegNum<[30]>;
def F15 : FPR<15, "f15">, DwarfRegNum<[31]>;
+// Status register
+def PSW : SystemZReg<"psw">;
+
/// Register classes
-def GR64 : RegisterClass<"SystemZ", [i64], 16,
+def GR64 : RegisterClass<"SystemZ", [i64], 64,
// Volatile registers
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R12, R13,
// Frame pointer, sometimes allocable
def FP64 : RegisterClass<"SystemZ", [f64], 64,
[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15]>;
+
+// Status flags registers.
+def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> {
+ let CopyCost = -1; // Don't allow copying of status registers.
+}