Refactor code into a new method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19635 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index a8e383060f03bbfe9a5b576512b5cc1f374d6153..95da4600db502a62efc7cf2ba7e17c3e1b3e8e33 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -567,8 +567,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     assert(VT == N1.getValueType() &&
            "Shift operators return type must be the same as their first arg");
     assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) &&
-           "Shifts only work on integers");
-    assert(VT >= MVT::i8 && "Shift amount cannot be a MVT::i1");
+           VT != MVT::i1 && "Shifts only work on integers");
     break;
   default: break;
   }

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index f747b35cf8d40d5c68d677806cdd7e0f6042de00..64940aa6b6c5d26125b2190ddef4ce2348a12854 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -806,30 +806,41 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
   return DAG.getCopyToReg(DAG.getRoot(), Op, Reg);
 }
 
-void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
-       std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
-                                    FunctionLoweringInfo &FuncInfo) {
-  SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
-
-  std::vector<SDOperand> UnorderedChains;
-  
+void SelectionDAGISel::
+LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
+               std::vector<SDOperand> &UnorderedChains) {
   // If this is the entry block, emit arguments.
-  Function *F = LLVMBB->getParent();
-  if (LLVMBB == &F->front()) {
+  Function &F = *BB->getParent();
+
+  if (BB == &F.front()) {
     // FIXME: If an argument is only used in one basic block, we could directly
     // emit it (ONLY) into that block, not emitting the COPY_TO_VREG node.  This
     // would improve codegen in several cases on X86 by allowing the loads to be
     // folded into the user operation.
-    std::vector<SDOperand> Args = TLI.LowerArguments(*LLVMBB->getParent(), DAG);
+    std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
+
+    FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
 
     unsigned a = 0;
-    for (Function::aiterator AI = F->abegin(), E = F->aend(); AI != E; ++AI,++a)
+    for (Function::aiterator AI = F.abegin(), E = F.aend(); AI != E; ++AI,++a)
       if (!AI->use_empty()) {
         SDL.setValue(AI, Args[a]);
         UnorderedChains.push_back(
                  CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]));
       }
   }
+}
+
+
+void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
+       std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
+                                    FunctionLoweringInfo &FuncInfo) {
+  SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
+
+  std::vector<SDOperand> UnorderedChains;
+  
+  // Lower any arguments needed in this block.
+  LowerArguments(LLVMBB, SDL, UnorderedChains);
 
   BB = FuncInfo.MBBMap[LLVMBB];
   SDL.setCurrentBasicBlock(BB);