/// @name Auto-generated Match Functions
/// {
- unsigned ComputeAvailableFeatures(const ARMSubtarget *Subtarget) const;
-
- bool MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>
- &Operands,
- MCInst &Inst);
+#define GET_ASSEMBLER_HEADER
+#include "ARMGenAsmMatcher.inc"
/// }
LLVMInitializeARMAsmLexer();
}
+#define GET_REGISTER_MATCHER
+#define GET_MATCHER_IMPLEMENTATION
#include "ARMGenAsmMatcher.inc"
}
};
-}
+} // end anonymous namespace
-static unsigned MatchRegisterName(StringRef Name);
+#define GET_REGISTER_MATCHER
+#include "X86GenAsmMatcher.inc"
AsmToken X86AsmLexer::LexTokenATT() {
AsmToken lexedToken = lexDefinite();
RegisterAsmLexer<X86AsmLexer> X(TheX86_32Target);
RegisterAsmLexer<X86AsmLexer> Y(TheX86_64Target);
}
-
-#define REGISTERS_ONLY
-#include "X86GenAsmMatcher.inc"
-#undef REGISTERS_ONLY
/// @name Auto-generated Matcher Functions
/// {
-
- unsigned ComputeAvailableFeatures(const X86Subtarget *Subtarget) const;
-
- bool MatchInstructionImpl(
- const SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCInst &Inst);
-
+
+#define GET_ASSEMBLER_HEADER
+#include "X86GenAsmMatcher.inc"
+
/// }
public:
MCInst &Inst) {
assert(!Operands.empty() && "Unexpect empty operand list!");
- X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
- assert(Op->isToken() && "Leading operand should always be a mnemonic!");
-
// First, try a direct match.
if (!MatchInstructionImpl(Operands, Inst))
return false;
// type. However, that requires substantially more matcher support than the
// following hack.
+ X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
+ assert(Op->isToken() && "Leading operand should always be a mnemonic!");
+
// Change the operand to point to a temporary token.
StringRef Base = Op->getToken();
SmallString<16> Tmp;
LLVMInitializeX86AsmLexer();
}
+#define GET_REGISTER_MATCHER
+#define GET_MATCHER_IMPLEMENTATION
#include "X86GenAsmMatcher.inc"
EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
+ // Information for the class declaration.
+ OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
+ OS << "#undef GET_ASSEMBLER_HEADER\n";
+ OS << " unsigned ComputeAvailableFeatures(const " <<
+ Target.getName() << "Subtarget *Subtarget) const;\n";
+ OS << "bool MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
+ << " &Operands, MCInst &Inst);\n\n";
+ OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
+
+
+
+
+ OS << "\n#ifdef GET_REGISTER_MATCHER\n";
+ OS << "#undef GET_REGISTER_MATCHER\n\n";
+
// Emit the subtarget feature enumeration.
EmitSubtargetFeatureFlagEnumeration(Target, Info, OS);
// Emit the function to match a register name to number.
EmitMatchRegisterName(Target, AsmParser, OS);
+
+ OS << "#endif // GET_REGISTER_MATCHER\n\n";
- OS << "#ifndef REGISTERS_ONLY\n\n";
+
+ OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
+ OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
// Generate the unified function to convert operands into an MCInst.
EmitConvertToMCInst(Target, Info.Instructions, OS);
<< "; it != ie; ++it) {\n";
// Emit check that the required features are available.
- OS << " if ((AvailableFeatures & it->RequiredFeatures) "
- << "!= it->RequiredFeatures)\n";
- OS << " continue;\n";
-
+ OS << " if ((AvailableFeatures & it->RequiredFeatures) "
+ << "!= it->RequiredFeatures)\n";
+ OS << " continue;\n";
+
// Emit check that the subclasses match.
for (unsigned i = 0; i != MaxNumOperands; ++i) {
OS << " if (!IsSubclass(Classes["
<< i << "], it->Classes[" << i << "]))\n";
OS << " continue;\n";
}
+
OS << "\n";
OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
OS << " return true;\n";
OS << "}\n\n";
- OS << "#endif // REGISTERS_ONLY\n";
+ OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
}