ath9k: Enable Fractional N mode
authorSujith <Sujith.Manoharan@atheros.com>
Thu, 12 Feb 2009 04:36:45 +0000 (10:06 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 27 Feb 2009 19:51:43 +0000 (14:51 -0500)
This patch enables Fractional N mode for all channel
if the EEPROM says so, and also fixes the INI only
when the device is not a 2 GHz only capable device.

Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath9k/eeprom.c
drivers/net/wireless/ath9k/eeprom.h
drivers/net/wireless/ath9k/hw.c
drivers/net/wireless/ath9k/phy.c

index 34e9d818faddeee7f34c28a613558023082fab2c..68de89d7986fc584ac90415c7c86ce202311b3e9 100644 (file)
@@ -466,6 +466,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
                return pBase->txMask;
        case EEP_RX_MASK:
                return pBase->rxMask;
+       case EEP_FRAC_N_5G:
+               return 0;
        default:
                return 0;
        }
@@ -1599,6 +1601,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
                        return pBase->dacHiPwrMode_5G;
                else
                        return 0;
+       case EEP_FRAC_N_5G:
+               if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
+                       return pBase->frac_n_5g;
+               else
+                       return 0;
        default:
                return 0;
        }
index 5c0d6c339fe9db8bc35a6a848406b608f29b132e..60cb23de97c6cada94a4830ae75d70b18fdb958b 100644 (file)
 #define AR5416_EEP_MINOR_VER_17      0x11
 #define AR5416_EEP_MINOR_VER_19      0x13
 #define AR5416_EEP_MINOR_VER_20      0x14
+#define AR5416_EEP_MINOR_VER_22      0x16
 
 #define AR5416_NUM_5G_CAL_PIERS         8
 #define AR5416_NUM_2G_CAL_PIERS         4
@@ -188,6 +189,7 @@ enum eeprom_param {
        EEP_RXGAIN_TYPE,
        EEP_TXGAIN_TYPE,
        EEP_DAC_HPWR_5G,
+       EEP_FRAC_N_5G
 };
 
 enum ar5416_rates {
@@ -232,7 +234,9 @@ struct base_eep_header {
        u8 txGainType;
        u8 rcChainMask;
        u8 desiredScaleCCK;
-       u8 futureBase_3[23];
+       u8 power_table_offset;
+       u8 frac_n_5g;
+       u8 futureBase_3[21];
 } __packed;
 
 struct base_eep_header_4k {
index 55d5a7440942e7375606b76533c0600fd4eb2b6c..6939e4142325f5315457985b7b5e96f5106397f9 100644 (file)
@@ -823,7 +823,16 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
        if (AR_SREV_9280_20(ah))
                ath9k_hw_init_txgain_ini(ah);
 
-       if (ah->hw_version.devid == AR9280_DEVID_PCI) {
+       if (!ath9k_hw_fill_cap_info(ah)) {
+               DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
+               ecode = -EINVAL;
+               goto bad;
+       }
+
+       if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
+           test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
+
+               /* EEPROM Fixup */
                for (i = 0; i < ah->iniModes.ia_rows; i++) {
                        u32 reg = INI_RA(&ah->iniModes, i, 0);
 
@@ -838,13 +847,6 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
                }
        }
 
-       if (!ath9k_hw_fill_cap_info(ah)) {
-               DPRINTF(sc, ATH_DBG_RESET,
-                       "failed ath9k_hw_fill_cap_info\n");
-               ecode = -EINVAL;
-               goto bad;
-       }
-
        ecode = ath9k_hw_init_macaddr(ah);
        if (ecode != 0) {
                DPRINTF(sc, ATH_DBG_RESET,
index 52aa2a7abe7aa8b189f07fe32ea33c29363b81c1..e1494bae0f9fdc7d3f6d08f341c101c2a03f0a90 100644 (file)
@@ -132,20 +132,27 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
                bMode = 0;
                fracMode = 0;
 
-               if ((freq % 20) == 0) {
-                       aModeRefSel = 3;
-               } else if ((freq % 10) == 0) {
-                       aModeRefSel = 2;
-               } else {
+               switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
+               case 0:
+                       if ((freq % 20) == 0) {
+                               aModeRefSel = 3;
+                       } else if ((freq % 10) == 0) {
+                               aModeRefSel = 2;
+                       }
+                       if (aModeRefSel)
+                               break;
+               case 1:
+               default:
                        aModeRefSel = 0;
-
                        fracMode = 1;
                        refDivA = 1;
                        channelSel = (freq * 0x8000) / 15;
 
                        REG_RMW_FIELD(ah, AR_AN_SYNTH9,
                                      AR_AN_SYNTH9_REFDIVA, refDivA);
+
                }
+
                if (!fracMode) {
                        ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
                        channelSel = ndiv & 0x1ff;