#define LPSS_GENERAL_LTR_MODE_SW BIT(2)
#define LPSS_SW_LTR 0x10
#define LPSS_AUTO_LTR 0x14
+#define LPSS_TX_INT 0x20
+#define LPSS_TX_INT_MASK BIT(1)
struct lpss_shared_clock {
const char *name;
struct clk *clk;
};
+struct lpss_private_data;
+
struct lpss_device_desc {
bool clk_required;
const char *clkdev_name;
unsigned int prv_offset;
bool clk_gate;
struct lpss_shared_clock *shared_clock;
+ void (*setup)(struct lpss_private_data *pdata);
};
static struct lpss_device_desc lpss_dma_desc = {
const struct lpss_device_desc *dev_desc;
};
+static void lpss_uart_setup(struct lpss_private_data *pdata)
+{
+ unsigned int tx_int_offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
+ u32 reg;
+
+ reg = readl(pdata->mmio_base + tx_int_offset);
+ writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + tx_int_offset);
+}
+
static struct lpss_device_desc lpt_dev_desc = {
.clk_required = true,
.prv_offset = 0x800,
.clk_gate = true,
};
+static struct lpss_device_desc lpt_uart_dev_desc = {
+ .clk_required = true,
+ .prv_offset = 0x800,
+ .ltr_required = true,
+ .clk_gate = true,
+ .setup = lpss_uart_setup,
+};
+
static struct lpss_device_desc lpt_sdio_dev_desc = {
.prv_offset = 0x1000,
.ltr_required = true,
.prv_offset = 0x800,
.clk_gate = true,
.shared_clock = &uart_clock,
+ .setup = lpss_uart_setup,
};
static struct lpss_shared_clock spi_clock = {
{ "INT33C1", (unsigned long)&lpt_dev_desc },
{ "INT33C2", (unsigned long)&lpt_dev_desc },
{ "INT33C3", (unsigned long)&lpt_dev_desc },
- { "INT33C4", (unsigned long)&lpt_dev_desc },
- { "INT33C5", (unsigned long)&lpt_dev_desc },
+ { "INT33C4", (unsigned long)&lpt_uart_dev_desc },
+ { "INT33C5", (unsigned long)&lpt_uart_dev_desc },
{ "INT33C6", (unsigned long)&lpt_sdio_dev_desc },
{ "INT33C7", },
}
}
+ if (dev_desc->setup)
+ dev_desc->setup(pdata);
+
adev->driver_data = pdata;
ret = acpi_create_platform_device(adev, id);
if (ret > 0)