[ARM] Rename v8.1a from "extension" to "architecture"

v8.1a is renamed to architecture, following current entity naming approach.

Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233811 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 9babf4b3ad7cb63e89ec9555f87b675b8a6fbad4..9bbe40148155da36c60a6191b3a4971ed5750381 100644 (file)
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -175,7 +175,7 @@ def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
                                    "Support ARM v8 instructions",
                                    [HasV7Ops, FeatureVirtualization,
                                     FeatureMP]>;
-def FeatureV8_1a : SubtargetFeature<"v8.1a", "HasV8_1a", "true",
+def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
                                    "Support ARM v8.1a instructions",
                                    [HasV8Ops, FeatureAClass, FeatureCRC]>;
 
@@ -452,14 +452,6 @@ def : ProcessorModel<"cyclone",     SwiftModel,
                                      FeatureDB,FeatureDSPThumb2,
                                      FeatureHasRAS, FeatureZCZeroing]>;
 
-// V8.1 Processors
-def : ProcNoItin<"generic-armv8.1-a", [HasV8Ops, FeatureV8_1a,
-                                       FeatureDB, FeatureFPARMv8,
-                                       FeatureNEON, FeatureDSPThumb2,
-                                       FeatureHWDiv, FeatureHWDivARM,
-                                       FeatureTrustZone, FeatureT2XtPk,
-                                       FeatureCrypto]>;
-
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 3f41f62ad326fe780bb0597ae0e5644d91a3b2e4..49bd3d1c09f25a9559cffc4f5a434f0af1a9e10c 100644 (file)
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -661,8 +661,8 @@ void ARMAsmPrinter::emitAttributes() {
     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
     if (STI.hasV8Ops())
       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
-                        STI.hasV8_1a() ? ARMBuildAttrs::AllowNeonARMv8_1a:
-                                         ARMBuildAttrs::AllowNeonARMv8);
+                        STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
+                                            ARMBuildAttrs::AllowNeonARMv8);
   } else {
     if (STI.hasFPARMv8())
       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index c3984cae2db2beb7e9a7f4572f693d2a5e22e668..5e9a2fbb8850818a78fc9090730ac3e726fb734a 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -208,6 +208,8 @@ def HasV8            : Predicate<"Subtarget->hasV8Ops()">,
                                  AssemblerPredicate<"HasV8Ops", "armv8">;
 def PreV8            : Predicate<"!Subtarget->hasV8Ops()">,
                                  AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
+def HasV8_1a         : Predicate<"Subtarget->hasV8_1aOps()">,
+                                 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
 def NoVFP            : Predicate<"!Subtarget->hasVFP2()">;
 def HasVFP2          : Predicate<"Subtarget->hasVFP2()">,
                                  AssemblerPredicate<"FeatureVFP2", "VFP2">;
@@ -226,8 +228,6 @@ def HasCrypto        : Predicate<"Subtarget->hasCrypto()">,
                                  AssemblerPredicate<"FeatureCrypto", "crypto">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
                                  AssemblerPredicate<"FeatureCRC", "crc">;
-def HasV8_1a         : Predicate<"Subtarget->hasV8_1a()">,
-                                 AssemblerPredicate<"FeatureV8_1a", "v8.1a">;
 def HasFP16          : Predicate<"Subtarget->hasFP16()">,
                                  AssemblerPredicate<"FeatureFP16","half-float">;
 def HasDivide        : Predicate<"Subtarget->hasDivide()">,

diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 430b41028fe203942120f111f8f9bd83cba10dbd..dba2a2d27a4201bcb97bb4c0b21010add7e0a919 100644 (file)
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -133,6 +133,7 @@ void ARMSubtarget::initializeEnvironment() {
   HasV6T2Ops = false;
   HasV7Ops = false;
   HasV8Ops = false;
+  HasV8_1aOps = false;
   HasVFPv2 = false;
   HasVFPv3 = false;
   HasVFPv4 = false;
@@ -166,7 +167,6 @@ void ARMSubtarget::initializeEnvironment() {
   HasTrustZone = false;
   HasCrypto = false;
   HasCRC = false;
-  HasV8_1a = false;
   HasZeroCycleZeroing = false;
   AllowsUnalignedMem = false;
   Thumb2DSP = false;

diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index aaa35614f1ee77a01033640166bafbce6d3366c9..b8e8242fe95ff48c64216ab7572bdf3bf62784d1 100644 (file)
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -67,6 +67,7 @@ protected:
   bool HasV6T2Ops;
   bool HasV7Ops;
   bool HasV8Ops;
+  bool HasV8_1aOps;
 
   /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
   /// floating point ISAs are supported.
@@ -182,9 +183,6 @@ protected:
   /// HasCRC - if true, processor supports CRC instructions
   bool HasCRC;
 
-  /// HasV8_1a - if true, the processor has V8.1a: PAN and RDMA extensions
-  bool HasV8_1a;
-
   /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
   /// particularly effective at zeroing a VFP register.
   bool HasZeroCycleZeroing;
@@ -292,6 +290,7 @@ public:
   bool hasV6T2Ops() const { return HasV6T2Ops; }
   bool hasV7Ops()   const { return HasV7Ops;  }
   bool hasV8Ops()   const { return HasV8Ops;  }
+  bool hasV8_1aOps() const { return HasV8_1aOps; }
 
   bool isCortexA5() const { return ARMProcFamily == CortexA5; }
   bool isCortexA7() const { return ARMProcFamily == CortexA7; }
@@ -313,7 +312,6 @@ public:
   bool hasNEON() const { return HasNEON;  }
   bool hasCrypto() const { return HasCrypto; }
   bool hasCRC() const { return HasCRC; }
-  bool hasV8_1a() const { return HasV8_1a; }
   bool hasVirtualization() const { return HasVirtualization; }
   bool useNEONForSinglePrecisionFP() const {
     return hasNEON() && UseNEONForSinglePrecisionFP;

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 2215efb183634e9345f327db0589604e4f48c438..c1d2f7f3ee08e578cceae5c851831c772dec1c8d 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -276,8 +276,8 @@ class ARMAsmParser : public MCTargetAsmParser {
   bool hasD16() const {
     return STI.getFeatureBits() & ARM::FeatureD16;
   }
-  bool hasV8_1a() const {
-    return STI.getFeatureBits() & ARM::FeatureV8_1a;
+  bool hasV8_1aOps() const {
+    return STI.getFeatureBits() & ARM::HasV8_1aOps;
   }
 
   void SwitchMode() {

diff --git a/test/MC/ARM/basic-arm-instructions-v8.1a.s b/test/MC/ARM/basic-arm-instructions-v8.1a.s
index f46057b62d1803601e4e89c6b177dcdc52a88901..3101d19284ed6dfe83b65da61dca88db93c84a90 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions-v8.1a.s
+++ b/test/MC/ARM/basic-arm-instructions-v8.1a.s
@@ -43,28 +43,28 @@
   vqrdmlah.s16    d0, d1, d2
 //CHECK-V81aARM:   vqrdmlah.s16  d0, d1, d2      @ encoding: [0x12,0x0b,0x11,0xf3]
 //CHECK-V81aTHUMB: vqrdmlah.s16  d0, d1, d2      @ encoding: [0x11,0xff,0x12,0x0b]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlah.s16    d0, d1, d2
 //CHECK-V8:  ^
 
   vqrdmlah.s32  d0, d1, d2
 //CHECK-V81aARM:   vqrdmlah.s32  d0, d1, d2      @ encoding: [0x12,0x0b,0x21,0xf3]
 //CHECK-V81aTHUMB: vqrdmlah.s32  d0, d1, d2      @ encoding: [0x21,0xff,0x12,0x0b]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlah.s32  d0, d1, d2
 //CHECK-V8:  ^
 
   vqrdmlah.s16  q0, q1, q2
 //CHECK-V81aARM:   vqrdmlah.s16  q0, q1, q2      @ encoding: [0x54,0x0b,0x12,0xf3]
 //CHECK-V81aTHUMB: vqrdmlah.s16  q0, q1, q2      @ encoding: [0x12,0xff,0x54,0x0b]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlah.s16  q0, q1, q2
 //CHECK-V8:  ^
 
   vqrdmlah.s32  q2, q3, q0
 //CHECK-V81aARM:   vqrdmlah.s32  q2, q3, q0      @ encoding: [0x50,0x4b,0x26,0xf3]
 //CHECK-V81aTHUMB: vqrdmlah.s32  q2, q3, q0      @ encoding: [0x26,0xff,0x50,0x4b]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlah.s32  q2, q3, q0
 //CHECK-V8:  ^
 
@@ -72,28 +72,28 @@
   vqrdmlsh.s16  d7, d6, d5
 //CHECK-V81aARM:   vqrdmlsh.s16  d7, d6, d5      @ encoding: [0x15,0x7c,0x16,0xf3]
 //CHECK-V81aTHUMB: vqrdmlsh.s16  d7, d6, d5      @ encoding: [0x16,0xff,0x15,0x7c]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlsh.s16  d7, d6, d5
 //CHECK-V8:  ^
 
   vqrdmlsh.s32  d0, d1, d2
 //CHECK-V81aARM:   vqrdmlsh.s32  d0, d1, d2      @ encoding: [0x12,0x0c,0x21,0xf3]
 //CHECK-V81aTHUMB: vqrdmlsh.s32  d0, d1, d2      @ encoding: [0x21,0xff,0x12,0x0c]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlsh.s32  d0, d1, d2
 //CHECK-V8:  ^
 
   vqrdmlsh.s16  q0, q1, q2
 //CHECK-V81aARM:   vqrdmlsh.s16  q0, q1, q2      @ encoding: [0x54,0x0c,0x12,0xf3]
 //CHECK-V81aTHUMB: vqrdmlsh.s16  q0, q1, q2      @ encoding: [0x12,0xff,0x54,0x0c]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlsh.s16  q0, q1, q2
 //CHECK-V8:  ^
 
   vqrdmlsh.s32    q3, q4, q5
 //CHECK-V81aARM:   vqrdmlsh.s32  q3, q4, q5      @ encoding: [0x5a,0x6c,0x28,0xf3]
 //CHECK-V81aTHUMB: vqrdmlsh.s32  q3, q4, q5      @ encoding: [0x28,0xff,0x5a,0x6c]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlsh.s32  q3, q4, q5
 //CHECK-V8:  ^
 
@@ -119,28 +119,28 @@
   vqrdmlah.s16  d0, d1, d2[0]
 //CHECK-V81aARM:   vqrdmlah.s16 d0, d1, d2[0]    @ encoding: [0x42,0x0e,0x91,0xf2]
 //CHECK-V81aTHUMB: vqrdmlah.s16  d0, d1, d2[0]   @ encoding: [0x91,0xef,0x42,0x0e]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlah.s16  d0, d1, d2[0]
 //CHECK-V8:  ^
 
   vqrdmlah.s32  d0, d1, d2[0]
 //CHECK-V81aARM:   vqrdmlah.s32 d0, d1, d2[0]    @ encoding: [0x42,0x0e,0xa1,0xf2]
 //CHECK-V81aTHUMB: vqrdmlah.s32  d0, d1, d2[0]   @ encoding: [0xa1,0xef,0x42,0x0e]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlah.s32  d0, d1, d2[0]
 //CHECK-V8:  ^
 
   vqrdmlah.s16  q0, q1, d2[0]
 //CHECK-V81aARM:   vqrdmlah.s16  q0, q1, d2[0]   @ encoding: [0x42,0x0e,0x92,0xf3]
 //CHECK-V81aTHUMB: vqrdmlah.s16  q0, q1, d2[0]   @ encoding: [0x92,0xff,0x42,0x0e]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlah.s16  q0, q1, d2[0]
 //CHECK-V8:  ^
 
   vqrdmlah.s32  q0, q1, d2[0]
 //CHECK-V81aARM:   vqrdmlah.s32  q0, q1, d2[0]   @ encoding: [0x42,0x0e,0xa2,0xf3]
 //CHECK-V81aTHUMB: vqrdmlah.s32  q0, q1, d2[0]   @ encoding: [0xa2,0xff,0x42,0x0e]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlah.s32  q0, q1, d2[0]
 //CHECK-V8:  ^
 
@@ -148,27 +148,27 @@
   vqrdmlsh.s16  d0, d1, d2[0]
 //CHECK-V81aARM:   vqrdmlsh.s16 d0, d1, d2[0]    @ encoding: [0x42,0x0f,0x91,0xf2]
 //CHECK-V81aTHUMB: vqrdmlsh.s16  d0, d1, d2[0]   @ encoding: [0x91,0xef,0x42,0x0f]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlsh.s16  d0, d1, d2[0]
 //CHECK-V8:  ^
 
   vqrdmlsh.s32  d0, d1, d2[0]
 //CHECK-V81aARM:   vqrdmlsh.s32 d0, d1, d2[0]    @ encoding: [0x42,0x0f,0xa1,0xf2]
 //CHECK-V81aTHUMB: vqrdmlsh.s32  d0, d1, d2[0]   @ encoding: [0xa1,0xef,0x42,0x0f]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlsh.s32  d0, d1, d2[0]
 //CHECK-V8:  ^
 
   vqrdmlsh.s16  q0, q1, d2[0]
 //CHECK-V81aARM:   vqrdmlsh.s16 q0, q1, d2[0]    @ encoding: [0x42,0x0f,0x92,0xf3]
 //CHECK-V81aTHUMB: vqrdmlsh.s16  q0, q1, d2[0]   @ encoding: [0x92,0xff,0x42,0x0f]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlsh.s16  q0, q1, d2[0]
 //CHECK-V8:  ^
 
   vqrdmlsh.s32  q0, q1, d2[0]
 //CHECK-V81aARM:   vqrdmlsh.s32 q0, q1, d2[0]    @ encoding: [0x42,0x0f,0xa2,0xf3]
 //CHECK-V81aTHUMB: vqrdmlsh.s32  q0, q1, d2[0]   @ encoding: [0xa2,0xff,0x42,0x0f]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
 //CHECK-V8:  vqrdmlsh.s32  q0, q1, d2[0]
 //CHECK-V8:  ^