Disable bogus cast elimination when the cast is used by a setcc instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17583 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 5314dada04a5d90e195169a88fe49c36169fc01d..1dd946a421f4f90abccbeef8f50d593c6a7d7a46 100644 (file)
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -3163,15 +3163,15 @@ void PPC32ISel::visitCastInst(CastInst &CI) {
   // emit them, as the store instruction will implicitly not store the zero or
   // sign extended bytes.
   if (SrcClass <= cInt && SrcClass >= DestClass) {
-    bool AllUsesAreStoresOrSetCC = true;
+    bool AllUsesAreStores = true;
     for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
-      if (!isa<StoreInst>(*I) && !isa<SetCondInst>(*I)) {
-        AllUsesAreStoresOrSetCC = false;
+      if (!isa<StoreInst>(*I)) {
+        AllUsesAreStores = false;
         break;
       }        
     // Turn this cast directly into a move instruction, which the register
     // allocator will deal with.
-    if (AllUsesAreStoresOrSetCC) { 
+    if (AllUsesAreStores) { 
       unsigned SrcReg = getReg(Op, BB, MI);
       BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
       return;