struct uart_port port;\r
struct platform_device *pdev;\r
struct clk *clk;\r
+ struct clk *pclk;\r
unsigned int tx_loadsz; /* transmit fifo load size */\r
unsigned char ier;\r
unsigned char lcr;\r
\r
up->mcr = 0;\r
\r
+ clk_enable(up->pclk);\r
clk_enable(up->clk); // enable the config uart clock\r
\r
/*\r
\r
free_irq(up->port.irq, up);\r
clk_disable(up->clk);\r
+ clk_disable(up->pclk);\r
}\r
\r
static void\r
container_of(port, struct uart_rk_port, port);\r
\r
dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");\r
- if (state)\r
+ if (state) {\r
clk_disable(up->clk);\r
- else\r
+ clk_disable(up->pclk);\r
+ } else {\r
+ clk_enable(up->pclk);\r
clk_enable(up->clk);\r
+ }\r
}\r
\r
static void serial_rk_release_port(struct uart_port *port)\r
\r
sprintf(up->name, "rk29_serial.%d", pdev->id);\r
up->pdev = pdev;\r
+ up->pclk = clk_get(&pdev->dev, "pclk_uart");\r
up->clk = clk_get(&pdev->dev, "uart");\r
if (unlikely(IS_ERR(up->clk))) {\r
ret = PTR_ERR(up->clk);\r
up->port.membase = NULL;\r
do_put_clk:\r
clk_put(up->clk);\r
+ clk_put(up->pclk);\r
do_free:\r
kfree(up);\r
do_release_region:\r
iounmap(up->port.membase);\r
up->port.membase = NULL;\r
clk_put(up->clk);\r
+ clk_put(up->pclk);\r
kfree(up);\r
release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
}\r