rk3188: support hdmi 576p(dclk_lcdc freediv when need 27 MHz)

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index eeac5f89e0ff76dd6d6e2d7047a2aff203ba23c2..72da5601d357a911d9216286a96214576b28511e 100755 (executable)
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -1549,9 +1549,14 @@ static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
 
 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
 {
+       if (rate == 27 * MHZ)
+               return clkset_rate_freediv_autosel_parents(clk, rate);
+       else
+               return clkset_rate_evendiv_autosel_parents(clk, rate);
+
+#if 0
        int ret = 0;
        struct clk *parent;
-
        if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
                parent = clk->parents[1];
                //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
@@ -1576,13 +1581,14 @@ static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
                }
        }
        return ret;
+#endif
 }
 
 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
 static struct clk dclk_lcdc0 = {
        .name           = "dclk_lcdc0",
        .mode           = gate_mode,
-       .set_rate       = clkset_rate_evendiv_autosel_parents,
+       .set_rate       = dclk_lcdc_set_rate,
        .recalc         = clksel_recalc_div,
        .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
        .clksel_con     = CRU_CLKSELS_CON(27),
@@ -1595,7 +1601,7 @@ static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
 static struct clk dclk_lcdc1 = {
        .name           = "dclk_lcdc1",
        .mode           = gate_mode,
-       .set_rate       = clkset_rate_evendiv_autosel_parents,
+       .set_rate       = dclk_lcdc_set_rate,
        .recalc         = clksel_recalc_div,
        .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
        .clksel_con     = CRU_CLKSELS_CON(28),