return getMachineOpValue(MI, MI.getOperand(OpIdx));
}
+ // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
+ // TableGen'erated getBinaryCodeForInstr() function to encode any
+ // operand values, instead querying getMachineOpValue() directly for
+ // each operand it needs to encode. Thus, any of the new encoder
+ // helper functions can simply return 0 as the values the return
+ // are already handled elsewhere. They are placeholders to allow this
+ // encoder to continue to function until the MC encoder is sufficiently
+ // far along that this one can be eliminated entirely.
+ unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
+ const { return 0; }
+
/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
/// machine operand requires relocation, record the relocation and return
/// zero.
// Conditional code result for instructions whose 's' bit is set, e.g. subs.
def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
+ string EncoderMethod = "getCCOutOpValue";
let PrintMethod = "printSBitModifierOperand";
}
// Same as cc_out except it defaults to setting CPSR.
def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
+ string EncoderMethod = "getCCOutOpValue";
let PrintMethod = "printSBitModifierOperand";
}
list<dag> pattern>
: InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
bits<4> p; // Predicate operand
+ bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
let Inst{31-28} = p;
- // FIXME: The 's' operand needs to be handled, but the current generic
- // get-value handlers don't know how to deal with it.
+ let Inst{20} = s;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
/// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
+ /// getCCOutOpValue - Return encoding of the 's' bit.
+ unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const {
+ // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
+ // '1' respectively.
+ return MI.getOperand(Op).getReg() == ARM::CPSR;
+ }
+
unsigned getNumFixupKinds() const {
assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
return 0;
switch (Opcode) {
default: break;
case ARM::MOVi:
- // The 's' bit.
- if (MI.getOperand(4).getReg() == ARM::CPSR)
- Value |= 1 << ARMII::S_BitShift;
// The shifted immediate value.
Value |= getMachineSoImmOpValue((unsigned)MI.getOperand(1).getImm());
break;
case ARM::EORri:
case ARM::ORRri:
case ARM::SUBri:
- // The 's' bit.
- if (MI.getOperand(5).getReg() == ARM::CPSR)
- Value |= 1 << ARMII::S_BitShift;
// The shifted immediate value.
Value |= getMachineSoImmOpValue((unsigned)MI.getOperand(2).getImm());
break;
case ARM::EORrs:
case ARM::ORRrs:
case ARM::SUBrs: {
- // The 's' bit.
- if (MI.getOperand(7).getReg() == ARM::CPSR)
- Value |= 1 << ARMII::S_BitShift;
// The so_reg operand needs the shift ammount encoded.
unsigned ShVal = MI.getOperand(4).getImm();
unsigned ShType = ARM_AM::getShiftOpcEncoding(ARM_AM::getSORegShOp(ShVal));